If bus_dma will give us addresses > 32 bits, setup our dma tag
to accept up to 39bit addresses.
aic7770.c:
Update the softc directly rather than use an intermediate
"probe_config" structure.
aic7xxx.c:
Complete core work to support 39bit addresses for bulk data
dma operations. Controller data structures still must reside
under the 4GB boundary to reduce code/data size in the sequencer
and related data structures. This has been tested under Linux
IA64 and will be tested on IA64 for FreeBSD as soon as our port
can run there.
Add bus dmamap synchronization calls around manipulation of
all controller/kernel shared host data structures.
Implement data pointer reinitialation for a second data phase
in a single connection in the kernel rather than bloat the
sequencer. This is an extremely rare operation (does it ever
happen?) and the sequencer implementation was flawed for some
of the newest chips.
Don't ever allow our target role to initiate a PPR. This
is forbidden by the SCSI spec.
Add a few missing endian conversions in the ignore wide pointers
code. The core has been tested on the PPC under Linux and should
work for FreeBSD PPC. As soon as I can test the OSM layer for
FreeBSD PPC, I will.
Move some of ahc_softc_init() into ahc_alloc() now that the
probe_config structure is gone.
Add a 4GB boundary condition on all of our dma tags. 32bit
DAC under PCI only works on a single 4GB "page". Although
we can cross 4GB on a true 64bit bus, the card won't always
be installed in one and we can save code space and cost in
implementing high address support by assuming the high DWORD
address will never change.
Add diagnostics to ahc_search_qinfifo().
Correct a target mode issue with bus resets. To avoid an
interrupt storm from a malicious third party holding the
reset line, the sequencer would defer re-enabling the reset
interrupt until either a select-out or select-in. Unfortunately,
the select-in enable bit is cleared by a bus reset, so a second
reset will render the card deaf to an initiator's attempts to
contact it. We now re-enable bus reset interrupts immediately
if the target role is enabled.
aic7xxx.h:
Remove struct ahc_probe_config.
SCB's now contain a pointer to the sg_map_node so we can perfrom
bus dma sync operations on the SG list prior to queuing a command.
aic7xxx.reg:
Register the Perforce ID for this file with the VERSION keyword
so it is printed in generated files.
Add the DSCOMMAND1 register which is used to access the high
DWORD of address bits.
Add the data pointer reinitialize sequencer interrupt code.
aic7xxx.seq:
Register the Perforce ID for this file with the VERSION keyword
so it is printed in generated files.
Remove code to re-enable the bus reset interrupt after a select-in.
In target mode we cannot defer this operation as ENSELI is cleared
by a bus reset.
Complete 39bit support.
Generate a sequencer inteerrupt rather than handle the data
pointers re-initialitation in the sequencer.
Inline the "seen identify" assertion to save a few cycles.
Short circuit the update of our residual data if we have
fully completed a transfer. The residual is correct from
our last S/G load operation.
Short circuit full SDPTR processing if the residual is 0.
Just mark the transfer as complete.
aic7xxx_93cx6.c:
Synchronize perforce IDs.
aic7xxx_freebsd.c:
Complete untested 39bit support.
Add missing endia conversions.
Clear our residuals prior to starting a command. The
update residual code in the core only sets the residual
if there is one.
aic7xxx_freebsd.h:
Modeify ahc_dmamap_sync() macros to take an offset and a length.
This is how sync operations are performed in NetBSD, and we should
update our bus dma implementation to match.
aic7xxx_inline.h:
Add data structure synchronization helper functions.
Fix a bug in ahc_intr() where we would not clear our unsolicited
interrupt counter after running our PCI interrupt handler. This
may have been the cause of the spurious PCI interrupt messages.
aic7xxx_pci.c:
Adjust for loss of probe_config structure.
Guard against bogus 9005 subdevice information as seen on some
IBM MB configurations.
Add 39bit address support.
MFC after: 10 days
ahc_pci.c:
Prepare for making ahc a module by adding module dependency
and version info.
aic7770.c:
Remove linux header ifdefs. The headers are handled differently
in Linux where local includes (those using "'s instead of <>'s)
are allowed.
Don't map our interrupt until after we are fully setup to
handle interrupts. Our interrupt line may be shared so
an interrupt could occur at any time.
aic7xxx.c:
Remove linux header ifdefs.
current->curr to avoid Linux's use of current as a
#define for the current task on some architectures.
Add a helper function, ahc_assert_atn(), for use in
message phases we handle manually. This hides the fact
that U160 chips with the expected phase matching disabled
need to have SCSISIGO updated differently.
if (ahc_check_residual(scb) != 0)
ahc_calc_residual(scb);
else
ahc_set_residual(scb, 0);
becomes:
ahc_update_residual(scb);
Modify scsi parity error (or CRC error) handling to
reflect expected phase being disabled on U160 chips.
Move SELTO handling above BUSFREE handling so we can
use the new busfree interrupt behavior on U160 chips.
In ahc_build_transfer_msg() filter the period and ppr_options
prior to deciding whether a PPR message is required.
ppr_options may be forced to zero which will effect our
decision.
Correct a long standing but latent bug in ahc_find_syncrate().
We could choose a DT only rate even though DT transfers were
disabled. In the CAM environment this was unlikely as CAM
filters our rate to a non-DT value if the device does not
support such rates.
When displaing controller characteristics, include the
speed of the chip. This way we can modify the transfer
speed based on optional features that are enabled/disabled
in a particular application.
Add support for switching from fully blown tagged queing
to just using simple queue tags should the device reject
an ordered tag.
Remove per-target "current" disconnect and tag queuing
enable flags. These should be per-device and are not
referenced internally be the driver, so we let the OSM
track this state if it needs to.
Use SCSI-3 message terminology.
aic7xxx.h:
The real 7850 does not support Ultra modes, but there are
several cards that use the generic 7850 PCI ID even though
they are using an Ultra capable chip (7859/7860). We start
out with the AHC_ULTRA feature set and then check the
DEVSTATUS register to determine if the capability is really
present.
current -> curr
ahc_calc_residual() is no longer static allowing it to
be called from ahc_update_residual() in aic7xxx_inline.h.
Update some serial eeprom definitions for the latest
BIOS versions.
aic7xxx.reg:
Add a combined DATA_PHASE mask to the SCSIPHASE register
definition to simplify some sequencer code.
aic7xxx.seq:
Take advantage of some performance features available only
on the U160 chips. The auto-ack feature allows us to ack
data-in phases up to the data-fifo size while the sequencer
is still setting up the DMA engine. This greatly reduces
read transfer latency and simplifies testing for transfer
complete (check SCSIEN only). We also disable the expected
phase feature, and enable the new bus free interrupt behavior,
to avoid a few instructions.
Re-arrange the Ultra2+ data phase handling to allow us to
do more work in parallel with the data fifo flushing on a
read.
On an SDTR, ack the message immediately so the target can
prepare the next phase or message byte in parallel with
our work to honor the message.
aic7xxx_93cx6.c:
Remove linux header ifdefs.
aic7xxx_freebsd.c:
current -> curr
Add a module event handler.
Handle tag downgrades in our ahc_send_async() handler.
We won't be able to downgrade to "basic queuing" until
CAM is made aware of this queuing type.
aic7xxx_freebsd.h:
Include cleanups.
Define offsetof if required.
Correct a few comments.
Update prototype of ahc_send_async().
aic7xxx_inline.h:
Implement ahc_update_residual().
aic7xxx_pci.c:
Remove linux header ifdefs.
Correct a few product strings.
Enable several U160 performance enhancing features.
Modify Ultra capability determination so we will enable
Ultra speeds on devices with a 7850 PCI id that happen
to really be a 7859 or 7860.
Don't map our interrupt until after we are fully setup to
handle interrupts. Our interrupt line may be shared so
an interrupt could occur at any time.
aic7xxx_pci.c:
Enable board generation of interrupts only once our handler is
in place and all other setup has occurred.
aic7xxx.c:
More conversion of data types to ahc_* names. tmode_tstate and
tmode_lstate are the latest victims.
Clean up the check condition path by branching early rather
than indenting a giant block of code.
Add support for target mode initiated sync negotiation.
The code has been tested by forcing the feature on for
all devices, but for the moment is left inaccesible until
a decent mechanism for controlling the behavior is complete.
Implementing this feature required the removal of the
old "target message request" mechanism. The old method
required setting one of the 16 bit fields to initiate
negotiation with a particular target. This had the nice
effect of being easy to change the request and have it
effect the next command. We now set the MK_MESSAGE bit
on any new command when negotiation is required. When
the negotiation is successful, we walk through and clean
up the bit on any pending commands. Since we have to walk
the commands to reset the SCSI syncrate values so no additional
work is required. The only drawback of this approach is that
the negotiation is deferred until the next command is queued to
the controller. On the plus side, we regain two bytes of
sequencer scratch ram and 6 sequencer instructions.
When cleaning up a target mode instance, never remove the
"master" target mode state object. The master contains
all of the saved SEEPROM settings that control things like
transfer negotiations. This data will be cloned as the
defaults if a target mode instance is re-instantiated.
Correct a bug in ahc_set_width(). We neglected to update
the pending scbs to reflect the new parameters. Since
wide negotiation is almost always followed by sync
negotiation it is doubtful that this had any real
effect.
When in the target role, don't complain about
"Target Initiated" negotiation requests when an initiator
negotiates with us.
Defer enabling board interrupts until after ahc_intr_enable()
is called.
Pull all info that used to be in ahc_timeout for the FreeBSD
OSM into ahc_dump_card_state(). This info should be printed
out on all platforms.
aic7xxx.h:
Add the SCB_AUTO_NEGOITATE scb flag. This allows us to
discern the reason the MK_MESSAGE flag is set in the hscb
control byte. We only want to clear MK_MESSAGE in
ahc_update_pending_scbs() if the MK_MESSAGE was set due
to an auto transfer negotiation.
Add the auto_negotiate bitfield for each tstate so that
behavior can be controlled for each of our enabled SCSI
IDs.
Use a bus interrupt handler vector in our softc rather
than hard coding the PCI interrupt handler. This makes
it easier to build the different bus attachments to
the aic7xxx driver as modules.
aic7xxx.reg:
Remove the TARGET_MSG_REQUEST definition for sequencer ram.
aic7xxx.seq:
Fix a few target mode bugs:
o If MK_MESSAGE is set in an SCB, transition to
message in phase and notify the kernel so that
message delivery can occur. This is currently
only used for target mode initiated transfer
negotiation.
o Allow a continue target I/O to compile without
executing a status phase or disconnecting. If
we have not been granted the disconnect privledge
but this transfer is larger than MAXPHYS, it may
take several CTIOs to get the job done.
Remove the tests of the TARGET_MSG_REQUEST field in scratch ram.
aic7xxx_freebsd.c:
Add support for CTIOs that don't disconnect. We now defer
the clearing of our pending target state until we see a
CTIO for that device that has completed sucessfully.
Be sure to return early if we are in a target only role
and see an initiator only CCB type in our action routine.
If a CTIO has the CAM_DIS_DISCONNECT flag set, propogate
this flag to the SCB. This flag has no effect if we've
been asked to deliver status as well. We will complete
the command and release the bus in that case.
Handle the new auto_negotiate field in the tstate correctly.
Make sure that SCBs for "immediate" (i.e. to continue a non
disconnected transaction) CTIO requests get a proper mapping
in the SCB lookup table. Without this, we'll complain when
the transaction completes.
Update ahc_timeout() to reflect the changes to ahc_dump_card_state().
aic7xxx_inline.h:
Use ahc->bus_intr rather than ahc_pci_intr.
In our idle loop, use an or instruction to set PRELOADEN rather
than rewriting the contents of DMAPARAMS to DFCNTRL. The later
may re-enable the DMA engine if the idle loop is called to complete
the preload of at least one segment when a target disconnects on
an S/G segment boundary but before we have completed fetching the
next segment. This correts a hang, usually in message out phase,
when this situation occurs. This bug has been here for a long
time, so the situation is rare, but not impossible to reproduce.
It only affected Ultra2/U160 controllers.
Correct a few comments.
Extra Sanity. Make sure that SCSIEN is also turned off, along with
HDMAEN, at the end of the data phase.
aic7xxx.c:
Correct code that traverses the phase table. A much too quick
push to staticize this structure resulted in non-functional
lookup code. This corrects the printing of the phase where
a timeout occurred.
aic7xxx.reg:
Use FIFOQWDEMP as the name for bit 5 of DFSTATUS just like
the Adaptec data books.
aic7xxx.seq:
Refine the 2.1 PCI retry bug workaround for certain, non-ULTRA2,
controllers. When the DMA of an SCB completes, it can take
some time for HDONE to come true after MREQPEN (PCI memory request
pending) falls. If HDONE never comes true, we are in the hung
state and must manually drain the FIFO. We used to test HDONE for
3 clock cycles to detect this condition. This works on all of the
hardware I can personally test. Some controllers were reported
to take 4 clock cycles, so the last version of this code waited
4 clock cycles. This still didn't work for everyone. To fix this,
I've adjusted the work around so that even if the hardware hasn't
hung, but we run the work-around code, the result is a long winded
way to complete the transfer, rather than a hang.
ahc_eisa.c:
Change aic7770_map_int to take an additional irq parameter.
Although we can get the irq from the eisa dev under FreeBSD,
we can't do this under linux, so the OSM interface must supply
this.
ahc_pci.c:
Move ahc_power_state_change() to the OSM. This allows us to
use a platform supplied function that does the same thing.
-current will move to the FreeBSD native API in the near
future.
aic7770.c:
Sync up with core changes to support Linux EISA.
We now store a 2 bit primary channel number rather
than a bit flag that only allows b to be the primary
channel. Adjust for this change.
aic7xxx.c:
Namespace and staticization cleanup. All exported symbols
use an "ahc_" prefix to avoid collisions with other modules.
Correct a logic bug that prevented us from dropping
ATN during some exceptional conditions during message
processing.
Take advantage of a new flag managed by the sequencer
that indicates if an SCB fetch is in progress. If so,
the currently selected SCB needs to be returned to the
free list to prevent an SCB leak. This leak is a rarity
and would only occur if a bus reset or timeout resulting
in a bus reset occurred in the middle of an SCB fetch.
Don't attempt to perform ULTRA transfers on ultra capable
adapters missing the external precision resistor required
for ultra speeds. I've never encountered an adapter
configured this way, but better safe than sorry.
Handle the case of 5MHz user sync rate set as "0" instead of 0x1c
in scratch ram.
If we lookup a period of 0 in our table (async), clear the scsi offset.
aic7xxx.h:
Adjust for the primary channel being represented as
a 2 bit integer in the flags member of the ahc softc.
Cleanup the flags definitions so that comment blocks are
not cramped.
Update seeprom definitions to correctly reflect the fact
that the primary channel is represented as a 2 bit integer.
Add AHC_ULTRA_DIASABLED softc flag to denote controllers
missing the external precision resistor.
aic7xxx.reg:
Add DFCACHETH to the definition of DFSTATUS for completness sake.
Add SEQ_FLAGS2 which currently only contains the SCB_DMA
(SCB DMA in progress) flag.
aic7xxx.seq:
Correct a problem when one lun has a disconnected untagged
transaction and another lun has disconnected tagged transactions.
Just because an entry is found in the untagged table doesn't
mean that it will match. If the match on the lun fails, cleanup
the SCB (return it to the disconnected list or free it), and snoop
for a tag message. Before this change, we reported an unsolicited
reselection. This bug was introduced about a month ago during an
overly aggressive optimization pass on the reselection code.
When cleaning up an SCB, we can't just blindly free the SCB. In
the paging case, if the SCB came off of the disconnected list, its
state may never have been updated in host memory. So, check the
disconnected bit in SCB_CONTROL and return the SCB to the disconnected
list if appropriate.
Manage the SCB_DMA flag of SEQ_FLAGS2.
More carefully shutdown the S/G dma engine in all cases by using
a subroutine. Supposedly not doing this can cause an arbiter hang
on some ULTRA2 chips.
Formatting cleanup.
On some chips, at least the aic7856, the transition from
MREQPEND to HDONE can take a full 4 clock cycles. Test
HDONE one more time to avoid this race. We only want our
FIFO hung recovery code to execute when the engine is
really hung.
aic7xxx_93cx6.c:
Sync perforce ids.
aic7xxx_freebsd.c:
Adjust for the primary channel being a 2 bit integer
rather than a flag for 'B' channel being the primary.
Namespace cleanup.
Unpause the sequencer in one error recovery path that
neglected to do so. This could have caused us to perform
a bus reset when a recovery message might have otherwise been
successful.
aic7xxx_freebsd.h:
Use AHC_PCI_CONFIG for controlling compilation of PCI
support consistently throughout the driver.
Move ahc_power_state_change() to OSM.
aic7xxx_inline.h
Namespace cleanup.
Adjust our interrupt handler so it will work in the edge
interrupt case. We must process all interrupt sources
when the interrupt fires or risk not ever getting an
interrupt again. This involves marking the fact
that we are relying on an edge interrupt in ahc->flags
and checking for this condition in addition to the
AHC_ALL_INTERRUPTS flag. This fixes hangs on the
284X and any other aic7770 installation where level
interrupts are not available.
aic7xxx_pci.c:
Move the powerstate manipulation code into the OSM. Several
OSes now provide this functionality natively.
Take another shot at using the data stored in scratch ram
if the SCB2 signature is correct and no SEEPROM data is
available. In the past this failed if external SCB ram
was configured because the memory port was locked. We
now release the memory port prior to testing the values
in SCB2 and re-acquire it prior to doing termination control.
Adjust for new 2 bit primary channel setting.
Trust the STPWLEVEL setting on v 3.X BIOSes too.
Configure any 785X ID in the same fashion and assume
that any device with a rev id of 1 or higher has the
PCI 2.1 retry bug.
Use the target offset rather than the target Id to reference
the untagged SCB array. The offset and id are identical save
in the twin channel case. This should correct several issues
with the 2742T.
Set the user and goal settings prior to setting the current
settings. This allows the async update routine to filter out
intermediate transfer negotiation updates that may be less
than interesting. The Linux OSM uses this to reduce the amount
of stuff printed to the console.
aic7xxx.seq:
Correct an issue with the aic7770 in twin channel mode.
We could continually attempt to start a selection even
though a selection was already occurring on one channel.
This might have the side effect of hanging our selection
or causing us to select the wrong device.
While here, create a separate polling loop for when we
have already started a selection. This should reduce
the latency of our response to a (re)selection. The diffs
look larger than they really are due to some code rearrangement
to optimize out a jmp.
aic7xxx_freebsd.c:
Use the target offset rather than the target Id to reference
the untagged SCB array. The offset and id are identical save
in the twin channel case. This should correct several issues
with the 2742T.
aic7xxx_inline.h:
Get back in sync with perforce revision ID.
aic7xxx_pci.c:
Identify adapters in ARO mode as such.
Ensure that not only the subvendor ID is correct (9005)
but also that the controller type field is valid before
looking at other information in the subdevice id. Intel
seems to have decided that their subdevice id of 8086
is more appropriate for some of their MBs with aic7xxx
parts than Adaptec's sanctioned scheme.
Add an exclusion entry for SISL (AAC on MB based adapters).
Adapters in SISL mode are owned by the RAID controller, so
even if a driver for the RAID controller is not present,
it isn't safe for us to touch them.
Style nits.
Make sure that our selection hardware is disabled
as soon as possible after detecting a busfree and
even go so far as to disable the selection hardware
in advance of an event that will cause a busfree
(ABORT or BUS DEVICE RESET message). The concern
is that the selection hardware will select a target
for which, after processing the bus free, there
will be no commands pending. The sequencer idle
loop will re-enable the selection should it still be
necessary.
In ahc_handle_scsiint(), clear SSTAT0 events several
PCI transactions (most notably reads) prior to clearing
SCSIINT. The newer chips seem to take a bit of time to
see the change which can make the clearing of SCSIINT
ineffective.
Don't bother panicing at the end of ahc_handle_scsiint().
Getting to the final else just means we lost the race
with clearing SCSIINT.
In ahc_free(), handle init-level 0. This can happen when we
fail the attach for RAID devices. While I'm here, also kill
the parent dma tag.
In ahc_match_scb(), consider initiator ccbs to be any
that are not from the target mode group. This fixes
a bug where an external target reset CCB was not getting
cleaned up by the reset code.
Don't bother freezing a ccb in any of our "abort" routines
when the status is set to CAM_REQ_CMP. This can happen
for a target reset ccb.
aic7xxx.reg:
Reserve space for a completion queue. This will be used
to enhance performance in the near future.
aic7xxx.seq:
Remove an optimization for the 7890 autoflush bug that
turned out to allow, in rare cases, some data to get
lost.
Implement a simpler, faster, fix for the PCI_2_1 retry
bug that hangs the sequencer on an SCB dma for certain chips.
Test against SAVED_SCSIID rather than SELID during target
reselections. This is how we always did it in the past,
but the code was modified while trying to work around an
issue with the 7895. SAVED_SCSIID takes into account
twin channel adapters such as the 2742T, whereas SELID
does not have the channel bit. This caused invalid
selection warnings and other strangeness on these cards.
aic7xxx_pci.c
Use the correct mask for checking the generic aic7892
entry.
Initialize rid to 0. This doesn't seem to make any difference
(the driver doesn't care what rid it gets and no-one seems to
check rid's value), but follows standard conventions.
Pass in our device_t to ahc_alloc(). We now use device_T
softc storage, so passing NULL results in a panic.
Set the unit number in our softc so that the driver core
can retrieve it.
ahc_pci.c:
Set the unit number in our softc so that the driver core
can retrieve it.
aic7770.c:
Insert our softc into the list of softcs when initialization
is successful.
aic7xxx.c:
Remove a workaround for an aic7895 bug we will never trigger.
Add additional diagnostic info to ahc_dump_card_state().
Always panic the system if a sequencer assertion fails.
AHC_SCB_BTT is a "flag" not a "feature". Check the right
field in the softc.
Replace a hard coded number with a constant.
Guard against looping forever in ahc_pause_and_flushwork().
A hot eject or card failure may make the intstat register
return 0xFF, so limit the number of interrupts we'll process.
Correct the code in ahc_search_qinfifo() that guarantees that
the sequencer will see an abort collision if the qinfifo is
modified when a DMA is in progress. We now do this fixup
after modifying the queue. This guarantees that the HSCB
we place at the head of the queue is not the same as the
old head. Using "next hscb" (guaranteed not to be the
same as the first SCB) before clearing the queue could free
up the original head hscb to be used during a remove operation
placing it again at the head of the qinfifo.
aic7xxx.h:
Reduce the maximum number of outstanding commands to 253 from
254. To handle our output queue correctly on machines that only
support 32bit stores, we must clear the array 4 bytes at a
time. To avoid colliding with a DMA write from the sequencer,
we must be sure that 4 slots are empty when we write to clear
the queue. This reduces us to 253 SCBs: 1 that just completed
and the known three additional empty slots in the queue that
preceed it. Yahoo was able to force this race on one of their
systems. Interrupts were disabled for such a time that the
entire output queue was filled (254 entries complete without
any processing), and our 32bit write to clear the status clobbered
one entry.
Add a feature tag for devices that are removable.
aic7xxx.reg:
Never use the sequencer interrupt value of 0xF0. We need
to guanrantee that an INTSTAT value of 0xFF can only occur
during card failure or a hot-eject.
Align the busy targets table with the begining of scratch
space. This seems to appease a chip bug in the aic7895.
aic7xxx.seq:
Be sure to disable select-out after a bus free event that occurs
early in a selection. If we don't disable select-out, we will
believe that it is enabled even though a new selection will never
occur.
Move the clearing of SELDI to just before a jump. This appeases
another chip bug of the aic7895.
Make the target mode command loop a bit more efficient.
AHC_SCB_BTT is a "flag" not a "feature". Check the right
field in the softc.
Properly cleanup the last SCB we tested against should we
fail to properly find an SCB for a reselection.
Add some additional sequencer debugging code.
aic7xxx_freebsd.c:
Limit the driver to 253 outstanding commands per adapter.
Guard against overflow in timeout handling.
aic7xxx_inline.h:
AHC_SCB_BTT is a "flag" not a "feature". Check the right
field in the softc.
aic7xxx_pci.c:
Set the removable feature for the apa1480 cardbus and the 29160C
Compact PCI card.
Don't report high byte termination information for narrow cards.
Use a PCI read rather than a questionable delay when fetching/setting
termination settings.
ahc_pci.c:
Add detach support.
Make use of soft allocated on our behalf by newbus.
For PCI devices, disable the mapping type we aren't
using for extra protection from rogue code.
aic7xxx_93cx6.c:
aic7xxx_93cx6.h:
Sync perforce IDs.
aic7xxx_freebsd.c:
Capture the eventhandle returned by EVENTHANDER_REGISTER
so we can kill the handler off during detach.
Use AHC_* constants instead of hard coded numbers in a
few more places.
Test PPR option state when deciding to "really" negotiate
when the CAM_NEGOTIATE flag is passed in a CCB.
Make use of core "ahc_pause_and_flushwork" routine in our
timeout handler rather than re-inventing this code.
Cleanup all of our resources (really!) in ahc_platform_free().
We should be all set to become a module now.
Implement the core ahc_detach() routine shared by all of
the FreeBSD front-ends.
aic7xxx_freebsd.h:
Softc storage for our event handler.
Null implementation for the ahc_platform_flushwork() OSM
callback. FreeBSD doesn't need this as XPT callbacks are
safe from all contexts and are done directly in ahc_done().
aic7xxx_inline.h:
Implement new lazy interrupt scheme. To avoid an extra
PCI bus read, we first check our completion queues to
see if any work has completed. If work is available, we
assume that this is the source of the interrupt and skip
reading INTSTAT. Any remaining interrupt status will be
cleared by a second call to the interrupt handler should
the interrupt line still be asserted. This drops the
interrupt handler down to a single PCI bus read in the
common case of I/O completion. This is the same overhead
as in the not so distant past, but the extra sanity of
perforning a PCI read after clearing the command complete
interrupt and before running the completion queue to avoid
missing command complete interrupts added a cycle.
aic7xxx.c:
During initialization, be sure to initialize all scratch
ram locations before they are read to avoid parity errors.
In this case, we use a new function, ahc_unbusy_tcl() to
initialize the scratch ram busy target table.
Replace instances of ahc_index_busy_tcl() used to unbusy
a tcl without looking at the old value with ahc_unbusy_tcl().
Modify ahc_sent_msg so that it can find single byte messages.
ahc_sent_msg is now used to determine if a transfer negotiation
attempt resulted in a bus free.
Be more careful in filtering out only the SCSI interrupts
of interest in ahc_handle_scsiint.
Rearrange interrupt clearing code to ensure that at least
one PCI transaction occurrs after hitting CLRSINT1 and
writting to CLRINT. CLRSINT1 writes take a bit to
take effect, and the re-arrangement provides sufficient
delay to ensure the write to CLRINT is effective. The
old code might report a spurious interrupt on some "fast"
chipsets.
export ahc-update_target_msg_request for use by OSM code.
If a target does not respond to our ATN request, clear
it once we move to a non-message phase. This avoids
sending a MSG_NOOP in some later message out phase.
Use max lun and max target constants instead of
hard-coded values.
Use softc storage built into our device_t under FreeBSD.
Fix a bug in ahc_free() that caused us to delete
resources that were not allocated.
Clean up any tstate/lstate info in ahc_free().
Clear the powerdown state in ahc_reset() so that
registers can be accessed.
Add a preliminary function for pausing the chip and
processing any posted work.
Add a preliminary suspend and resume functions.
aic7xxx.h:
Limit the number of supported luns to 64. We don't
support information unit transfers, so this is the
maximum that makes sense for these chips.
Add a new flag AHC_ALL_INTERRUPTS that forces the
processing of all interrupt state in a single invokation
of ahc_intr(). When the flag is not set, we use the
lazy interrupt handling scheme.
Add data structures to store controller state while
we are suspended.
Use constants instead of hard coded values where appropriate.
Correct some harmless "unsigned/signed" conflicts.
aic7xxx.seq:
Only perform the SCSIBUSL fix on ULTRA2 or newer controllers.
Older controllers seem to be confused by this.
In target mode, ignore PHASEMIS during data phases.
This bit seems to be flakey on U160 controllers acting
in target mode.
aic7xxx_pci.c:
Add support for the 29160C CPCI adapter.
Add definitions for subvendor ID information
available for devices with the "9005" vendor id.
We currently use this information to determine
if a multi-function device doesn't have the second
channel hooked up on a board.
Add rudimentary power mode code so we can put the
controller into the D0 state. In the future this
will be an OSM callback so that in FreeBSD we don't
duplicate functionality provided by the PCI code.
The powerstate code was added after I'd completed
my regression tests on this code.
Only capture "left over BIOS state" if the POWRDN
setting is not set in HCNTRL.
In target mode, don't bother sending incremental
CRC data.
Shutdown the card when a catastrophic error occurs. This quenches
any interrupts stemming from the card.
aic7xxx_inline.h:
Return instead of processing additional interrupt state
after handling a catastrophic error. We now shutdown the
chip in this case in the hopes that the system can live
without this controller. The shutdown process invalidates any
other interrupt state.
aic7xxx.seq:
Only attempt to clear SCSIBUSL on Ultra2 controllers. The
clearing is workaround for a selection timeout bug on U2/U160
controllers and happens to be illegal on aic7770 (EISA/VL)
controllers.
numerous error recovery buglets.
Many thanks to Tor Egge for his assistance in diagnosing problems with
the error recovery code.
aic7xxx.c:
Report missed bus free events using their own sequencer interrupt
code to avoid confusion with other "bad phase" interrupts.
Remove a delay used in debugging. This delay could only be hit
in certain, very extreme, error recovery scenarios.
Handle transceiver state changes correctly. You can now
plug an SE device into a hot-plug LVD bus without hanging
the controller.
When stepping through a critical section, panic if we step
more than a reasonable number of times.
After a bus reset, disable bus reset interupts until we either
our first attempt to (re)select another device, or another device
attemps to select us. This removes the need to busy wait in
kernel for the scsi reset line to fall yet still ensures we
see any reset events that impact the state of either our initiator
or target roles. Before this change, we had the potential of
servicing a "storm" of reset interrupts if the reset line was
held for a significant amount of time.
Indicate the current sequencer address whenever we dump the
card's state.
aic7xxx.reg:
Transceiver state change register definitions.
Add the missed bussfree sequencer interrupt code.
Re-enable the scsi reset interrupt if it has been
disabled before every attempt to (re)select a device
and when we have been selected as a target.
When being (re)selected, check to see if the selection
dissappeared just after we enabled our bus free interrupt.
If the bus has gone free again, go back to the idle loop
and wait for another selection.
Note two locations where we should change our behavior
if ATN is still raised. If ATN is raised during the
presentation of a command complete or disconnect message,
we should ignore the message and expect the target to put
us in msgout phase. We don't currently do this as it
requires some code re-arrangement so that critical sections
can be properly placed around our handling of these two
events. Otherwise, we cannot guarantee that the check of
ATN is atomic relative to our acking of the message in
byte (the kernel could assert ATN).
Only set the IDENTIFY_SEEN flag after we have settled
on the SCB for this transaction. The kernel looks at
this flag before assuming that SCB_TAG is valid. This
avoids confusion during certain types of error recovery.
Add a critical section around findSCB. We cannot allow
the kernel to remove an entry from the disconnected
list while we are traversing it. Ditto for get_free_or_disc_scb.
aic7xxx_freebsd.c:
Only assume that SCB_TAG is accurate if IDENTIFY_SEEN is
set in SEQ_FLAGS.
Fix a typo that caused us to execute some code for the
non-SCB paging case when paging SCBs. This only occurred
during error recovery.
When restarting the sequencer, ensure that the SCBCNT register
is 0. A non-zero count will prevent the setting of the CCSCBDIR
bit in any future dma operations. The only time CCSCBCNT would
be non-zero is if we happened to halt the dma during a reset,
but even that should never happen. Better safe than sorry.
When a command completes before the target responds to an
ATN for a recovery command, we now notify the kernel so that
any recovery operation requeued in the qinfifo can be removed
safely. In the past, we did this in ahc_done(), but ahc_done()
may be called without the card paused. This also avoids a
recursive call to ahc_search_qinifo() which could have occurred if
ahc_search_qinififo() happened to be the routine to complete
a recovery action.
Fix 8bit math used for adjusting the qinfifo. The index must
be wrapped properly within the 256 entry array. We rely on the
fact that qinfifonext is a uint8_t in most cases to handle
this wrap, but we missed a few spots where the resultant
calculation was promoted to an int.
Change the way that we deal with aborting the first or second
entry from the qinfifo. We now swap the first entry in the
qinfifo with the "next queued scb" to force the sequencer
to see an abort collision if we ever touch the qinififo while
the sequencer is mid SCB dma.
aic7xxx.reg:
Add new MKMSG_FAILED sequencer interrupt. This displaced
the BOGUS_TAG interrupt used in some previous sequencer code
debugging.
aic7xxx.seq:
Increment our position in the qinfifo only once the dma
is complete and we have verified that the queue has not
been changed during our DMA. This simplifies code in the
kernel.
Protect against "instruction creep" when issuing a pausing
sequencer interrupt. On at least the 7890/91/96/97, the
sequencer will coast after issuing the interrupt for up
to two instructions. In the past we delt with this by
using carefully placed nops. Now we call a routine to
issue the interrupt followed by a nop and a ret.
Tell the kernel should an SCB complete with the MK_MESSAGE
flag still set. This means the target ignored our ATN request.
Clear the channel twice as we exit the data phase. On the
aic7890/91, the S/G preload logic may require the second
clearing to get the last S/G out of the FIFO.
aic7xxx_freebsd.c:
Don't bother searching the qinfifo for a doubly queued
recovery scb in ahc_done. This case is handled by the
core driver now.
Free the path used to issue async callbacks after the callback
is complete.
aic7xxx_inline.h:
Split the SCB queue routine into a routine that swaps
the SCB with the "next queued SCB" and a routine that
calls the swapping routine and notifies the card of
the new SCB. The swapping routine is now also used by
ahc_search_qinfifo.
Filter incoming transfer negotiation requests to ensure they
never exceed the settings specified by the user.
In restart sequencer attempt to deal with a bug in the aic7895.
If a third party reset occurs at just the right time, the
stack register can lock up. When restarting the sequencer
after handling the SCSI reset, poke SEQADDR1 before resting
the sequencers program counter.
When something strange happens, dump the card's transaction
state via ahc_dump_card_state(). This should aid in debugging.
Handle request sense transactions via the QINFIFO instead of
attaching them to the waiting queue directly. The waiting
queue consumes card SCB resources and, in the pathological case
of every target on the bus beating our selection attemps and
issuing a check condition, could have caused us to run out
of SCBs. I have never seen this happen, and only early
cards with 3 or 4 SCBs had any real chance of ever getting
into this state.
Add additional sequencer interrupt codes to support firmware
diagnostics. The diagnostic code is enabled with the
AHC_DEBUG_SEQUENCER kernel option.
Make it possible to switch into and out of target mode on
the fly. The card comes up by default as an initiator but
will switch into target mode as soon as an enable lun operation
is performed. As always, target mode behavior is gated
by the AHC_TMODE_ENABLE kernel option so most users will
not be affected by this change.
In ahc_update_target_msg_request(), also issue a new
request if the ppr_options have changed.
Never issue a PPR as a target. It is forbidden by the spec.
Correct a bug in ahc_parse_msg() that prevented us from
responding to PPR messages as a target.
Mark SCBs that are on the untagged queue with a flag instead
of checking several fields in the SCB to see if the SCB should
be on the queue. This makes it easier for things like automatic
request sense requests to be queued without touching the
untagged queues even though they are untagged requests.
When dealing with ignore wide residue messages that occur
in the middle of a transfer, reset HADDR, not SHADDR for
non-ultra2 chips. Although SHADDR is where the firmware
fetches the ending transfer address for a save data pointers
request, it is readonly. Setting HADDR has the side effect
of also updating SHADDR.
Cleanup the output of ahc_dump_card_state() by nulling out the
free scb list in the non-paging case. The free list is only
used if we must page SCBs.
Correct the transmission of cdbs > 12 bytes in length. When
swapping HSCBs prior to notifing the sequencer of the new
transaction, the bus address pointer for the cdb must also
be recalculated to reflect its new location. We now defer
the calculation of the cdb address until just before queing
it to the card.
When pulling transfer negotiation settings out of scratch
ram, convert 5MHz/clock doubled settings to 10MHz.
Add a new function ahc_qinfifo_requeue_tail() for use by
error recovery actions and auto-request sense operations.
These operations always occur when the sequencer is paused,
so we can avoid the extra expense incurred in the normal
SCB queue method.
Use the BMOV instruction for all single byte moves on
controllers that support it. The bmov instruction is
twice as fast as an AND with an immediate of 0xFF as
is used on older controllers.
Correct a few bugs in ahc_dump_card_state(). If we have
hardware assisted queue registers, use them to get the
sequencer's idea of the head of the queue. When enumerating
the untagged queue, it helps to use the correct index for
the queue.
aic7xxx.h:
Indicate via a feature flag, which controllers can take
on both the target and the initiator role at the same time.
Add the AHC_SEQUENCER_DEBUG flag.
Add the SCB_CDB32_PTR flag used for dealing with cdbs
with lengths between 13 and 32 bytes.
Add new prototypes.
aic7xxx.reg:
Allow the SCSIBUSL register to be written to. This is
required to fix a selection timeout problem on the 7892/99.
Cleanup the sequencer interrupt codes so that all debugging
codes are grouped at the end of the list.
Correct the definition of the ULTRA_ENB and DISC_DSB locations
in scratch ram. This prevented the driver from properly honoring
these settings when no serial eeprom was available.
Remove an unused sequencer flag.
aic7xxx.seq:
Just before a potential select-out, clear the SCSIBUSL
register. Occasionally, during a selection timeout, the
contents of the register may be presented on the bus,
causing much confusion.
Add sequencer diagnostic code to detect software and or
hardware bugs. The code attempts to verify most list
operations so any corruption is caught before it occurs.
We also track information about why a particular reconnection
request was rejected.
Don't clobber the digital REQ/ACK filter setting in SXFRCTL0
when clearing the channel.
Fix a target mode bug that would cause us to return busy
status instead of queue full in respnse to a tagged transaction.
Cleanup the overrun case. It turns out that by simply
butting the chip in bitbucket mode, it will ack any
bytes until the phase changes. This drasticaly simplifies
things.
Prior to leaving the data phase, make sure that the S/G
preload queue is empty.
Remove code to place a request sense request on the waiting
queue. This is all handled by the kernel now.
Change the semantics of "findSCB". In the past, findSCB
ensured that a freshly paged in SCB appeared on the disconnected
list. The problem with this is that there is no guarantee that
the paged in SCB is for a disconnected transation. We now
defer any list manipulation to the caller who usually discards
the SCB via the free list.
Inline some busy target table operations.
Add a critical section to protect adding an SCB to
the disconnected list.
aic7xxx_freebsd.c:
Handle changes in the transfer negotiation setting API
to filter incoming requests. No filtering is necessary
for "goal" requests from the XPT.
Set the SCB_CDB32_PTR flag when queing a transaction with
a large cdb.
In ahc_timeout, only take action if the active SCB is
the timedout SCB. This deals with the case of two
transactions to the same device with different timeout
values.
Use ahc_qinfifo_requeu_tail() instead of home grown
version.
aic7xxx_inline.h:
Honor SCB_CDB32_PTR when queuing a new request.
aic7xxx_pci.c:
Use the maximum data fifo threshold for all chips.
aic7xxx.c:
In target mode, reset the TQINPOS on every restart of the sequencer.
In the past we did this only during a bus reset, but there are other
reasons the sequencer might be reset.
In ahc_clear_critical_section(), disable pausing chip interrupts while
we step the sequencer out of a critical section. This avoids the
possibility of getting a pausing interrupt (unexpected bus free,
bus reset, etc.) that would prevent the sequencer from stepping.
Send the correct async notifications in the case of a BDR or bus reset.
In ahc_loadseq(), correct the calculation of our critical sections.
In some cases, the sections would be larger than needed.
aic7xxx.h:
Remove an unused SCB flag.
aic7xxx.seq:
MK_MESSAGE is cleared by the kernel, there is no need to waste
a sequencer instruction clearing it.
aic7xxx_freebsd.c:
Go through the host message loop instead of issuing a single
byte message directly in the ahc_timeout() case where we
are currently on the bus to the device. The effect is the same,
but this way we get a nice printf saying that an expected BDR
was delivered instead of an unexpected bus free.
If we are requeuing an SCB for an error recovery action, be sure
to set the DISCONNECTED flag in the in-core version of the SCB.
This ensures that, in the SCB-paging case, the sequencer will
still recognize the reselection as valid even if the version
of the SCB with this flag set was never previously paged out
to system memory. In the non-paging case, set the MK_MESSAGE
flag in SCB_CONTROL directly.
aic7xxx_pci.c:
Enable the Memeory Write and Invalidate bug workaround for
all aic7880 chips with revs < 1. This bug is rarely triggered
in FreeBSD as most transfers end on cache-aligned boundaries,
but a recheck of my references indicates that these chips
are affected.
of two (one to access the circular input fifo, the other to get the SCB).
This costs us a command slot so the driver can now only queue 254
simultaneous commands.
Have the kernel driver honor critical sections in sequencer code.
When prefetching S/G segments only pull a cacheline's worth but
never less than two elements. This reduces the impact of the
prefetch on the main data transfer when compared to the 128
byte fetches the driver used to do.
Add "bootverbose" logging for transfer negotiations.
Correct a bug in ahc_set_syncrate() that would prevent an update
of the sync parameters if only the ppr_options had changed.
Correct locking for calls to ahc_free_scb(). ahc_free_scb() is no
longer protected internally to simplify ports to other platforms.
Make sure we unfreeze our SIMQ if a resource shortage has occurred
and an SCB is been freed.
ahc_pci.c:
Turn on cacheline streaming for all controllers that support it.
Clarify diagnostic messages about PCI interrupts.
sequencer files. Different platforms place the included files in different
locations and it is easier to modify the include path passed as arguments
to the assembler than adding #ifdef support to the assembler.
Remove a spurious 'nop' instruction.
Separate our platform independent hooks from core driver functionality
shared between platforms (FreeBSD and Linux at this time).
Add sequencer workarounds for several chip->chipset interactions.
Correct external SCB corruption problem on aic7895 based cards (3940AUW).
Lots of cleanups resulting from the port to another OS.
Disable "cache line streaming" for aic7890/91 Rev A chips. I
have never seen these chips fail using this feature, but
some of Adaptec's regression tests have.
Explicitly set "cache line streaming" to on for aic7896/97
chips. This was happening before, but this documents the
fact that these chips will not function correctly without
CACHETHEEN set.
aic7xxx.h:
Add new bug types.
Fix a typo in a comment.
aic7xxx.reg:
Add a definition for the SHVALID bit in SSTAT3 for Ultra2/3
chips. This bit inicates whether the bottom most (current)
element in the S/G fifo has exhausted its data count.
aic7xxx.seq:
Be more careful in how we turn off the secondary DMA channel.
Being less careful may hang the PCI bus arbitor that negotiates
between the two DMA engines.
Remove an unecessary and incorrect flag set operation in
the overrun case.
On Ultra2/3 controllers, clear the dma FIFO before starting
to handle an overrun. We don't want any residual bytes from
the beginning of the overrun to cause the code that shuts
down the DMA engine from hanging because the FIFO is not
(and never will be) empty.
If the data fifo is empty by the time we notice that a
read transaction has completed, there is no need to
hit the flush bit on aic7890/91 hardware that will not
perform an auto-flush. Skip some cycles by short circuiting
the manual flush code in this case.
When transitioning out of data phase, make sure that we
have the next S/G element loaded for the following
reconnect if there is more work to do. The code
would do this in most cases before, but there was
a small window where the current S/G element could
be exhausted before our fetch of the next S/G element
completed. Since the S/G fetch is already initiated
at this point, it makes sense to just wait for the
segment to arrive instead of incuring even more latency
by canceling the fetch and initiating it later.
Fast path the end of data phase handling for the last
S/G segment. In the general case, we might have
worked ahead a bit by stuffing the S/G FIFO with
additional segments. If we stop before using them
all, we need to fixup our location in the S/G stream.
Since we can't work past the last S/G segment, no
fixups are ever required if we stop somewhere in
that final segment.
Fix a little buglet in the target mode dma bug handler.
We were employing the workaround in all cases instead
of only for the chips that require it.
Fix the cause of SCB timeouts and possible "lost data"
during read operations on the aic7890. When sending
a data on any Ultra2/3 controller, the final segment
must be marked as such so the FIFO will be flushed and
cleaned up correctly when the transfer is ended. We
failed to do this for the CDB transfer and so, if
the target immediately transfered from command to data
phase without an intervening disconnection, the first
segment transferred would be any residual bytes from
the cdb transfer. The Ultra160 controllers for some
reason were not affected by this problem.
Many Thanks to Tor Egge for bringing the aic7890 problem
to my attention, providing analysis, as well as a mechanism
to reproduce the problem.
Correct the BUILD_TCL macro. It was placing the target id
in the wrong bits. This was only an issue for adapters that
do not perform SCB paging (aha-3940AUW for instance).
Don't bother inlining ahc_index_busy_tcl. It is never
used in a performance critical path and is a bit chunky.
Correct ahc_index_busy_tcl to deal with "busy target tables"
embedded in the latter half of 64byte SCBs.
Don't initialize the busy target table to its empty state
until after we have finished extracting configuration
information from chip SRAM. In the common case of using
16 bytes of chip SRAM to do untagged target lookups,
we were trashing the last 8 targets configuration data.
(actually only target 8 because of the bug in the
BUILD_TCL macro).
Cram the "bus reset delivered" message back under bootverbose.
Fix the cleanup of the SCB busy target table when aborting
commands. If the lun is wildcarded, we must loop through
all possible luns.
aic7xxx.h:
Only bother supporting 64 luns right now. It doesn't seem
like either this driver or any peripherals will be doing
information unit transfers (where the lun number is a
32 bit integer) any time soon.
aic7xxx.seq:
Fix support for the aic7895. We must flush the data
FIFO if performing a manual transfer that is not
a multiple of 8 bytes. We were doing this quite
regularly for embedded cdbs.
Manaually flush the fifo on earlier adapters when
dealing with embedded cdbs too. We were stuffing
the FIFO with 16 bytes instead, but triggering
the flush is more efficient and allows us to
remove two instructions from the "copy_to_fifo"
routine.
other systems.
o Normalize copyright text.
o Clean up probe code function interfaces by passing around a single
structure of common arguments instead of passing "too many" args
in each function call.
o Add support for the AAA-131 as a SCSI adapter.
o Add support for the AHA-4944 courtesy of "Matthew N. Dodd" <winter@jurai.net
o Correct manual termination support for PCI cards. The bit definitions
for manual termination control in the SEEPROM were incorrect.
o Add support for extracting NVRAM information from SCB 2 for BIOSen
that use this mechanism to pass this data to OS drivers.
o Properly set the STPWLEVEL bit in PCI config space based on the
setting in an SEEPROM.
o Go back to useing 32byte SCBs for all controllers. The current
firmware allows us to embed 12byte cdbs on all controllers in
a 32byte SCB, and larger cdbs are rarely used, so it is a
better use of this space to offer more SCBs (32).
o Add support for U160 transfers.
o Add an idle loop executed during data transfers that prefetches
S/G segments on controllers that have a secondary DMA engine
(aic789X).
o Improve the performance of reselections by avoiding an extra
one byte DMA in the case of an SCB lookup miss for the reselecting
target. We now keep a 16byte "untagged target" array on the card
for dealing with untagged reselections. If the controller has
external SCB ram and can support 64byte SCBs, then we use an
"untagged target/lun" array to maximize concurrency. Without
external SCB ram, the controller is limited to one untagged
transaction per target, auto-request sense operations excluded.
o Correct the setup of the STPWEN bit in SXFRCTL1. This control
line is tri-stated until set to one, so set it to one and then
set it to the desired value.
o Add tagged queuing support to our target role implementation.
o Handle the common cases of the ignore wide residue message
in firmware.
o Add preliminary support for 39bit addressing.
o Add support for assembling on big-endian machines. Big-endian
support is not complete in the driver.
o Correctly remove SCBs in the waiting for selection queue when
freezing a device queue.
o Now that we understand more about the autoflush bug on the
aic7890, only use the workaround on devices that need it.
o Add a workaround for the "aic7890 hangs the system when you
attempt to pause it" problem. We can now pause the aic7890
safely regardless of what instruction it is executing.
negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets
where not properly updated when the DT entry was added and so
the driver could attempt to negotiate a speed faster than that
supported by the target device or even requested by the user
via SCSI-Select settings. *
o Update the target mode incoming command queue kernel index value
ever 128 commands instead of 32. This means that the kernel will
always try to keep its index (as seen on the card - the kernel may
actually have cleared more space) 128 commands ahead of where the
sequencer is adding entries.
o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location
in SRAM to indicate the kernel's target queue possition on Ultra2
cards. This avoids the "pause bug" on these cards and also turns
out to be much more efficient.
o When enabling or disabling a particular target id for target mode,
make sure that the taret id in the SCSIID register does not
reference an ID that is not to receive target selections. This
is only an issue on chips that support the multiple target id
feature where the value in SCSIID will still affect selection
behavior regardless of the values in the target id bit field
registers.
o Remove some target mode debugging printfs.
o Make sure that the sense length reported in ATIO commands is
always zero. This driver does not, yet, report HBA generated
sense information for accepted commands.
o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for
the CCB timeout field.
o Make the driver compile with AHC_DEBUG again.
* Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
for optimizing the unpause operation no-longer exist, and this is much
safer.
When restarting the sequencer, reconstitute the free SCB list on the card.
This deals with a single instruction gap between marking the SCB as free
and actually getting it onto the free list.
Reduce the number of transfer negotiations that occur. In the past, we
renegotiated after every reported check condition status. This ensures
that we catch devices that have unexpectidly reset. In this situation,
the target will always report the check condition before performing a
data-phase. The new behavior is to renegotiate for any check-condition where
the residual matches the orginal data-length of the command (including
0 length transffers). This avoids renegotiations during things like
variable tape block reads, where the check condition is reported only
to indicate the residual of the read.
Revamp the parity error detection logic. We now properly report and
handle injected parity errors in all phases. The old code used to hang
on message-in parity errors.
Correct the reporting of selection timeout errors to the XPT. When
a selection timeout occurs, only the currently selecting command
is flagged with SELTO status instead of aborting all currently active
commands to that target.
Fix flipped arguments in ahc_match_scb and in some of the callers of this
routine. I wish that gcc allowed you to request warnings for enums passed
as ints.
Make ahc_find_msg generically handle all message types.
Work around the target mode data-in wideodd bug in all non-U2 chips.
We can now do sync-wide target mode transfers in target mode across the
hole product line.
Use lastphase exclusively for handling timeouts. The current phase
doesn't take the bus free state into account.
Fix a bug in the timeout handler that could cause corruption of the
disconnected list.
When sending an embedded cdb to a target, ensure that we start on a
quad word boundary in the data-fifo. It seems that unaligned stores
do not work correctly.
93cx6.c:
Make the SRAM dump output a little prettier.
aic7xxx.c:
Store all SG entries into our SG array in kernel space.
This makes data-overrun and other error reporting more
useful as we can dump all SG entries. In the past,
we only stored the SG entries that the sequencer might
need to access, which meant we skipped the first element
that is embedded into the SCB.
Add a table of chip strings and replace ugly switch
statements with table lookups.
Add a table with bus phase strings and message reponses
to parity errors in those phases. Use the table to
pretty print bus phase messages as well as collapse
another switch statement.
Fix a bug in target mode that could cause us to unpause
the sequencer early in bus reset processing.
Add the 80MHz/DT mode into our syncrate table. This
rate is not yet used or enabled.
Correct some comments, clean up some code...
aic7xxx.h:
Add U160 controller feature information.
Add some more bit fields for various SEEPROM formats.
aic7xxx.reg:
Add U160 register and register bit definitions.
aic7xxx.seq:
Make phasemis state tracking more straight forward. This
avoids the consumption of SINDEX which is a very useful register.
For the U160 chips, you must use the 'mov' instruction to
update DFCNTRL. Using 'or' to set the PRELOADED bit is
completely ineffective.
At the end of the command phase, wair for our ACK signal
to de-assert before disabling the SCSI dma engine. For
slow devices, this avoids clearing the ACK before the
other end has had a chance to see it and lower REQ.
aic7xxx.c:
Add a function for sucking firmware out of the controller
prior to reset.
Remove some inline bloat from functions that should not have
been inlined.
During initialization, wait 1ms after the chip reset before
touching any registers. You can get machine checks on certain
architectures (Atari I think?) without the delay.
Return CAM_REQ_CMP for external BDR requests instead
of CAM_BDR_SENT.
Bump some messages to bootverbose levels above 1.
Don't clear any negotiated sync rate if the target rejects
a WDTR message. The sync rate is only cleared if the target
accepts a WDTR message.
Fix a small bug in the mesgin handling code that could cause
us to believe that we had recieved a message that was actually
received by another target. This could only confuse us in
some very rare transmission negotiation scenarios.
Remove some unecessary cleanup of residual information after
a residual is reported. The sequencer does this when the
command is queued now.
aic7xxx parts. This problem could result in data corruption
during periods of my PCI bus load by busmasters other than the
aic7xxx.
Many thanks to Andrew Gallatin <gallatin@cs.duke.edu> for characterizing
the symptoms of this problem and testing this fix.
Honor the 'bus reset at startup' option now that the XPT properly
handles transfer negotiation in this scenario.
Honor the sync rate settings on Ultra2 controllers. We would
always negotiate at the fastest speed. Oops.
aic7xxx.h:
Whitespace.
aic7xxx.seq:
Fix a minor nit that would cause the controller to miss the update
of the negotiation required bitmask causing the negotiation to
be delayed by a command.
tell the sequencer to pause itself for a target msg variable update. This
avoids the pause race entirely as HS_MAILBOX can be accessed without
pausing the chip.
3.2 Merge candidate.
Don't mess with the IRQMS bit in the host control register unless
we are an aic7770 chip.
Use calling context to determine if the card is already paused when
we update the target message request bit field in controller scratch
ram. Looking at the paused bit in the HCNTRL register opened up a
race condition.
Insert delays in the target message request update routine as a temporary
work around for what looks like a chip bug. I'm still investigating this
one.
Fix the Abort/Abort Tag/BDR handler to pull its message from the message
buffer in our softc instead of attempting to get it from a register on
the controller. The message is never recorded by the controller in the
new message scheme.
Don't rely on having an SCB when a BDR occurs. We can issue these during
invalid reconnects to.
Fix a few cases where we were restarting the sequencer but then still
falling out of a switch statement to unpause the sequencer again.
This could cause us to mess up sequencer state if it generated another
pausing interrupt between the time of the restart and unpause.
Kill the 'transceiver settle' loop during card initialization. I
failed to realize that a controller that is not connected to any
cables will never settle or enable the SCSI transceivers at all.
The correct solution is to monitor the IOERR interrupt which indicates
that the transceiver state has changed (UW<->LVD).
Modify the aic7xxx assembler to properly echo input when stdin is not
a tty.
connection.
Clean up support for devices featuring the multiple target SCSI ID feature.
On aic7890/91/96/97 chips, we can now assume the target role on multiple
target ids simultaneously. Although these chips also have sufficient
instruction space to hold to support the initiator and target role at the
same time, the initiator role is currently disabled as it will conflict
(chip design restriction) with the multi-tid feature. I'll probably add
a nob to enable the initiator (there-by disabling multi-tid) some time
in the future.
Return queue full or busy, depending on the tagged nature of the incoming
request, if our command input queue fills up in host memeory.
Deal with accept target I/O resource shortages.
If we get an underrun on a transaction that wasn't supposed to transmit
any data, don't attempt to print out the S/G list. The code would
run until hitting a non-present page. (oops)
black hole device. The controller will now only accept selections if
the black hole device is present and some other target/lun is enabled
for target mode.
Handle the IGNORE WIDE RESIDUE message. This support has not been tested.
Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS,
and CLEAR QUEUE messages as a target.
Fix a few problems with tagged command handling in target mode.
Wait until the sync offset counter falls to 0 before changing phase
after a data-in transfer completes as the DMA logic seems to indicate
transfer complete as soon as our last REQ is issued.
Simplify some of the target mode message handling code in the sequencer.
Use the host message loop for any unknown message types instead of performing
a reject message in the sequencer. Pass reject messages to the host
message loop too which frees up a sequencer interrupt type slot.
Default to issuing a bus reset if initiator mode is enabled. It seems
that the reset scsi bus bit is not defined in the same location for
all aic78xx BIOSes, so attempting to honor this setting will have to
wait until I get more information on how to detect it.
Nuke some unused variables.
in target mode, but we are not completing the command.
Use a template of allowed bus arbitration phases to selectively and
dynamically enable/disable initiator or target (re)selection.
Properly handle timeouts for target role transactions - just go to the
bus free state and report the error to the peripheral driver.
Checkpoint support for the XPT_ABORT_CCB function code. This currently
handles the accept tio and immediate notify ccb types, but does not
handle the continue target I/O or SCSI I/O ccb types. This is enough
to handle dynamic target enable/disable events.
Clean up the SCSI reset code so that we perform at most 1 SCSI bus
reset at initialization, the reset requested by the XPT layer.
is more robust and common code can be used for both the target and iniator
roles. The mechanism for tracking negotiation state has also been simplified.
Add support for sync/wide negotiation in target mode and fix many of
the target mode bugs running at higher speeds uncovered. Make a first
stab at getting all of the bus skew delays correct. Sync+Wide dataout
transfers still cause problems, but this may be an initiator problem.
Ensure that we exit BITBUCKET mode if the controller is restarted.
Add support for target mode only firmware downloads. This has been
tested on the aic7880, but should mean that we can perform target mode
on any aic7xxx controller. Mixed mode (initiator and target roles in
the same firmware load) is currently only supported on the aic7890, but
with optimization, may fit on chips with less instruction space.
use a 256 entry ring buffer of descriptersfor this purpose. This allows
the use of a simple 8bit counter in the sequencer code for tracking start
location.
Entries in the ring buffer now contain a "cmd_valid" byte at their tail.
As an entry is serviced, this byte is cleared by the kernel and set by
the sequencer during its dma of a new entry. Since this byte is the last
portion of the command touched during a dma, the kernel can use this
byte to ensure the command it processes is completely valid.
The new command format requires a fixed sized DMA from the controller
to deliver which allowed for additional simplification of the sequencer
code. The hack that required 1 SCB slot to be stolen for incoming
command delivery notification is also gone.
- Convert to CAM
- Use a new DMA based queuing and paging scheme
- Add preliminary target mode support
- Add support for the aic789X chips
- Take advantage of external SRAM on more controllers.
- Numerous bug fixes and performance improvements.
data fifo is full, but the PCI input latch is not empty,
HDMAEN cannot be cleared. The fix used here is to attempt
to drain the data fifo until there is space for the input
latch to drain and HDMAEN de-asserts.
This is a 1 instruction fix, so it should have no performance
impact.
operands that are set during seqeuncer program download instead of at
assembly time.
Convert the sequencer code to use" downloaded constants" for four run time
constants that vary depending on the board type. This frees up 4 bytes
of sequencer scratch ram space where these constants used to be stored and
also removes the additional instructions required to load their values
into the accumulator prior to using them.
Remove the REJBYTE sram variable. The host driver can just as easly
read the accumulator to get this value.
The scratch ram savings is important as the old code used to clober the
SCSICONF register on 274X cards which sits near the top of scratch ram
space. The SCSICONF register controls bus termination, and clobbering
it is not a good thing. Now we have 4 bytes to spare.
This should fix the reported problems with cards that don't have devices
attached to them failing with a stream of "Somone reset bus X" messages.
Doug Ledford determined the cause of the problem, fixes by me.
entry to the QOUTFIFO when it is full. This should eliminate the
"Timed out while idle" problems that many have reported.
In truth, this is somewhat of a hack. Although are interrupt latency is
low enough that we should be able to always service the queue in time,
since each entry must be passed up to the higher SCSI layer for what can
be a large amount of processing (perhaps even resulting in a new command
being queued) with interrupts disabled, we need this mechanism to avoid
overflow. In the future, these additional tasks will be offloaded to a
software interrupt handler which should make this hack unnecessary.
if SCB Paging was enabled:
disconnect with more data to transfer
disconnected SCB gets paged out
target reconnects so we page SCB back in
target completes transfer so residual is 0
target disconnects
SCB gets reused but not paged out since the residual is 0 (optimization)
target reconnects so we page the SCB back in
we report a residual because of stale residual information.
The fix for this is to set a flag that forces the SCB to be paged back
up to the host if we page in an SCB with a residual
Pointed out by: Doug Ledford <dledford@dialnet.net>
to fix a selection timeout problem.
If we can't find an SCB for the reconnecting target, issue a bus device
reset as the SCSI2 spec suggests.
Add a missing call to "add_scb_to_free_list" in the non paging case. In
the non-paging case, the SCBs don't really need to be on the free list,
but putting them there clears the tag field which is something the recovery
code depends on.
Be consistant about testing for parity errors after waiting for a
REQ on the bus.
Don't ack the last byte in a transaction until after we've cleared
all target state.
aic7xxx_asm.c:
Test the return value of getopt against -1 not EOF. (Yet another
shameless victum of the style guide being wrong).
loop, test for them separately. The bug report from David Malone showed that
even though we had been reselected (SELDI was true), we sat in the poll for
work loop until the selection timeout timer expired. It may be that the
SSTAT0 register doesn't like to have more than one bit tested at a time.
I've seen stranger things than this on these parts.
