o Rename __start to __start_mips and change the args a little
o Create a new __start written in assembler that copes with the
different ABIs and rewrites the args a little to make their passing
more abi agnostic.
o Add an alias _start for __start for the Cavium toolchain (in the
cavium port, a custom ld script is used which references _start
instead of the traditional mips __start).
o call _init_tls() when we aren't being an a.out shared library (which
is the only time _DYNAMIC is != NULL, I think). We could likely
retire support for a.out shared libraries entirely, but that will be
in the future when I'm sure there's not some subtle reason to keep
them around.
# Note: the reason mips starts at __start instead of _start is purely
# historical, but I didn't want to change it here and in the
# toolchain. The Cavium build process is kind of the odd duck here,
# but it is trivial to support both, so why not...
In addition, add a work around for (or maybe you would call it
increase compatibility with) Cavium toolchain:
the .cprestore macro references fp rather than sp, so we need
to copy sp to fp in a couple of places.
Also add a couple of comments to explain what's going on.
Obtained from: Cavium FreeBSD/octeon port.
here yet, so I've not connected it to the build. I think that we'll
need to move something into the processor specific part of the mips
port by requiring mips_cpu_ptrace or platform_cpu_ptrace be provided
by the ports to get/set processor specific registers, ala SSE
registers on x86.
statement. When no caches support was added, it looks like
TARGET_OCTEON was bogusly moved inside the if. Also, include
opt_cputype.h to make TARGET_OCTEON actually active.
# now we die in pmap init somewhere... Most likely because 32MB of RAM is
# too tight given the load address we're using.
o Introduce a uart bus space so that we don't have to hack dev/uart to do 8
byte reads. This also handles the shift properly, so reset the shift we
want dev/uart doing to 0. In effect, this bus space makes the octeon
registers have an interface to dev/uart that looks just like the old ISA
bus, but does the necessary 64-bit read/write to the bus. We only support
read/write operations. We do all the widths, but likely could get away
with only 64-bit and 8-bit given the restricted nature of use of this bus.
o use bus_space_map to set the .bsh rather than a direct assignment.
o Minor cleanup of uart_cpu_getdev to make it conform more to the other
implementations.
o Add some coments for future work.
# with these changes, we now make it through cninit, but there's still some
# problem that's preventing output, as well as another problem that causes
# us to call panic just after we return from cninit() in platform_start.
cacheable window on physical memory (KSEG0). On the Sibyte processor
going through the uncacheable window (KSEG1) bypasses both L1 and L2
caches so we may end up with stale contents in the L2 cache.
This also makes it consistent with the rest of the function that
uses cacheable mappings to copy pages.
Approved by: imp (mentor)
fixed-state media with parameters set via hints
and configure MAC accordingly to these parameters.
All the underlying PHY magic is done by boot manager
on startup. At the moment there is no proper way
to make active and control all PHYs simultaneously
from one MII bus and there is no way to associate
incoming/outgoing packet with specific PHY.
original codes (I had changed one by accident)
Also do the pic_ack/pic_delayed_ack after the interrupt
so we clear it. The clock with these changes starts working.
Its off doing a short/long short/long warning but it
now runs.
My NFS mount now works but has the same problem with
sbin/init (errno 8 ENOEXEC) so it panics with no init.
Either this is a problem with my buildworld.. OR its a
yet undiscovered RMI issue.
