Commit Graph

25 Commits

Author SHA1 Message Date
Marcel Moolenaar
4827e0cd5c Make sure bus space accesses use unorder memory loads and stores.
Memory accesses are posted in program order by virtue of the
uncacheable memory attribute.
Since GCC, by default, adds acquire and release semantics to
volatile memory loads and stores, we need to use inline assembly
to guarantee it. With inline assembly, we don't need volatile
pointers anymore.

Itanium does not support semaphore instructions to uncacheable
memory.
2009-12-03 04:06:48 +00:00
Marcel Moolenaar
d3fc9d46d4 Add inline function ia64_fc_i() to abstract inline assembly.
Use the new inline function in ia64_invalidate_icache().
While there, add proper synchronization so that we know
the fc.i instructions have taken effect when we return.
2008-07-07 17:43:56 +00:00
Marcel Moolenaar
e54994f990 In ia64_set_rr(), don't perform data serialization. This allows
us to do the data serializations once after writing multiple
region registers, as is done in pmap_switch(). All existing
calls to ia64_set_rr() are followed with calls to ia64_srlz_d().

Approved by: re (blanket)
2007-08-05 18:19:38 +00:00
Marcel Moolenaar
855218fbd1 Add ia64_srlz_d() and ia64_srlz_i() functions to aid in serialization.
Approved by: re (blanket)
2007-08-04 19:26:42 +00:00
Marcel Moolenaar
9beb1d0779 Have the processor defer all faults and exceptions for control
speculative loads. This at least makes control speculative loads
work. In the future we should analyze which faults/exceptions
we want to handle rather than defer to avoid having to call the
recovery code when it's not strictly necessary.
2007-05-27 19:02:47 +00:00
Marcel Moolenaar
cbef4d0edc For ia64_ptc_{e,g,ga,l}(), use instruction serialization. We
typically don't know what the TLB described and need to assume
that it affects the fetching of instructions.
2005-08-06 19:54:31 +00:00
Marcel Moolenaar
b00555136c Add an instruction group break after the move to application register
and the move to control register to avoid dependency violations when
these functions are used. Note that explicit data and instruction
serialization also need to be in a subsequent instruction group.
This too requires that we have an igrp break here.
2003-08-15 05:46:33 +00:00
Marcel Moolenaar
ed4ee6b2af Enable the high FP registers when we call the FPSWA handler and disable
them again afterwards. This fixes a disabled FP fault while in the FPSWA
handler.
While here, merge the FP fault and FP trap handling code to reduce code
duplication. Where code was different, it was not sure it should be.

Trigger case: ports/math/atlas
2003-07-13 04:08:16 +00:00
Marcel Moolenaar
23c12a63cf o Remove namespace pollution from param.h:
-  Don't include ia64_cpu.h and cpu.h
   -  Guard definitions by  _NO_NAMESPACE_POLLUTION
   -  Move definition of KERNBASE to vmparam.h

o  Move definitions of IA64_RR_{BASE|MASK} to vmparam.h
o  Move definitions of IA64_PHYS_TO_RR{6|7} to vmparam.h

o  While here, remove some left-over Alpha references.
2002-05-19 04:42:19 +00:00
Doug Rabson
01426578dc Add definitions for IA-32 exceptions, interrupts and intercepts. 2002-04-10 19:22:45 +00:00
Doug Rabson
63fe680462 Define a complete set of accessors for application and control registers. 2002-04-09 09:03:30 +00:00
Doug Rabson
17ea508863 Add ia64_sync_i(), ia64_get_tpr() and ia64_set_tpr(). 2002-03-14 12:29:55 +00:00
Doug Rabson
378749743c Add data serialisations after ptc and mov to rr[] instructions. 2001-10-23 10:20:04 +00:00
Doug Rabson
f85321667c Add ia64_set_fpsr(). 2001-10-21 14:00:59 +00:00
Doug Rabson
c7521efc59 Add ia64_get_lid(). 2001-10-05 08:20:41 +00:00
Doug Rabson
85d6f9f7d3 Add ia64_fc(). 2001-09-21 10:09:27 +00:00
Doug Rabson
a5e2a508c7 Add ia64_get_cpuid(). 2001-09-18 15:21:18 +00:00
Doug Rabson
749520911b Add ia64_mf_a() which executes an mf.a instruction. 2001-09-15 12:30:19 +00:00
John Baldwin
409b7113a1 Add a inline function to read the psr. 2001-02-22 15:39:58 +00:00
Doug Rabson
ce97a5fc4e * Various fixes to breakage introduced by the atomic and mutex reorgs.
* Fixes to the signal delivery code. Not quite right yet.

I would have preferred to wait until I have signal delivery actually
working but the current kernel in CVS doesn't build.
2000-10-24 19:54:38 +00:00
Doug Rabson
61e1efff8a Implement a rudimentary interrupt handling system which should be good
enough for clock interrupts in SKI.
2000-10-12 17:47:01 +00:00
Doug Rabson
ec502c357d * Add rudimentary DDB support (no kgdb, no backtrace, no single step).
* Track recent changes to SWI code.
* Allocate RIDs for pmaps (untested).
* Implement assembler version of cpu_switch - its cleaner that way.
2000-10-10 14:57:10 +00:00
Doug Rabson
8d9761debf Next round of fixes to the ia64 code. This includes simulated clock and
disk drivers along with a load of fixes to context switching, fork
handling and a load of other stuff I can't remember now. This takes us as
far as start_init() before it dies. I guess now I will have to finish off
the VM system and syscall handling :-).
2000-10-04 17:53:03 +00:00
Doug Rabson
431f3cb41d Next round of ia64 work, including fixes to context switching,
implementing cpu_fork(), copy*str(), bcopy(), copy{in,out}(). With these
changes, my test kernel reaches the mountroot prompt.
2000-09-30 17:48:44 +00:00
Doug Rabson
1ebcad5720 This is the first snapshot of the FreeBSD/ia64 kernel. This kernel will
not work on any real hardware (or fully work on any simulator). Much more
needs to happen before this is actually functional but its nice to see
the FreeBSD copyright message appear in the ia64 simulator.
2000-09-29 13:46:07 +00:00