the chipset. This is already how the multi-hose systems handle resource
allocation and it fixes a bug where dense and bwx memory allocations were
not handled properly.
Reviewed by: gallatin
- Make softinterrupts (SWI's) almost completely MI, and divorce them
completely from the x86 hardware interrupt code.
- The ihandlers array is now gone. Instead, there is a MI shandlers array
that just contains SWI handlers.
- Most of the former machine/ipl.h files have moved to a new sys/ipl.h.
- Stub out all the spl*() functions on all architectures.
Submitted by: dfr
the drivers.
* Remove legacy inx/outx support from chipset and replace with macros
which call busspace.
* Rework pci config accesses to route through the pcib device instead of
calling a MD function directly.
With these changes it is possible to cleanly support machines which have
more than one independantly numbered PCI busses. As a bonus, the new
busspace implementation should be measurably faster than the old one.
tsunami systems and the PCI bus-numbering system of FreeBSD. Eg, the former
allows for 2 PCI bus 2's (one each on hoses 0 and 1) while the latter
needs to give each PCI bus a unique monotonically increasing number.
It has been fairly well tested and correctly maps machines with a ppb on
hose 1 as well as machines with ppbs on both hoses.
DS10s remain untested, as I do not have a pci card with a ppb which will
pass POST in a tsunami.
This is a house of cards.
device_add_child_ordered(). 'ivars' may now be set using the
device_set_ivars() function.
This makes it easier for us to change how arbitrary data structures are
associated with a device_t. Eventually we won't be modifying device_t
to add additional pointers for ivars, softc data etc.
Despite my best efforts I've probably forgotten something so let me know
if this breaks anything. I've been running with this change for months
and its been quite involved actually isolating all the changes from
the rest of the local changes in my tree.
Reviewed by: peter, dfr
can deal with from 1GB to 2GB. I have no way to test with >1GB because I
don't have high enough density memory to get any one box over 1GB. However, I
have tested it on xp1000 & ds10 with < 1GB of memory & have verified that it
does no harm.
Merge the contents (less some trivial bordering the silly comments)
of <vm/vm_prot.h> and <vm/vm_inherit.h> into <vm/vm.h>. This puts
the #defines for the vm_inherit_t and vm_prot_t types next to their
typedefs.
This paves the road for the commit to follow shortly: change
useracc() to use VM_PROT_{READ|WRITE} rather than B_{READ|WRITE}
as argument.
Rather than teaching pci_ioctl about hoses, we just pass down a magic number
& let the platform code figure out what the hose is based on what the bus
number is.
concept approved by dfr
(behind the built-in ppb on hose 1) to be found:
When testing the adaptec controller on alpha, I realized I misread the xp1000
documentation and the way I'm calculating the bus number for PCI
config space accesses on the tsunami is wrong. I had thought that a bus
behind a ppb should be numbered as the nth bus in that hose, but it
actually needs to be the nth global bus within the system. The bus number
for the primary bus on a hose must always remain 0 when calculating config
space addresses.
Compaq XP1000, AlphaServer DS20, AlphaServer DS10, and DP264
This has been tested *only* on XP1000's. I'll be interested to hear from
owners of other types of DEC_ST6600 alphas.
I'd like to thank Don Rice of Compaq for providing the documentation required
to support this platform on FreeBSD. I'd also like to thank Doug Rabson for newbus,
and for helping me get a multiple hoses working with newbus.
Reviewed by: Doug Rabson <dfr@nlsystems.com>
