Commit Graph

22 Commits

Author SHA1 Message Date
Andrey V. Elsukov
50f5c94edb Fix possible NULL pointer dereference in ffec_alloc_mbufcl().
PR:		231514
Approved by:	re (kib)
MFC after:	1 week
2018-09-21 13:44:05 +00:00
Matt Macy
d7c5a620e2 ifnet: Replace if_addr_lock rwlock with epoch + mutex
Run on LLNW canaries and tested by pho@

gallatin:
Using a 14-core, 28-HTT single socket E5-2697 v3 with a 40GbE MLX5
based ConnectX 4-LX NIC, I see an almost 12% improvement in received
packet rate, and a larger improvement in bytes delivered all the way
to userspace.

When the host receiving 64 streams of netperf -H $DUT -t UDP_STREAM -- -m 1,
I see, using nstat -I mce0 1 before the patch:

InMpps OMpps  InGbs  OGbs err TCP Est %CPU syscalls csw     irq GBfree
4.98   0.00   4.42   0.00 4235592     33   83.80 4720653 2149771   1235 247.32
4.73   0.00   4.20   0.00 4025260     33   82.99 4724900 2139833   1204 247.32
4.72   0.00   4.20   0.00 4035252     33   82.14 4719162 2132023   1264 247.32
4.71   0.00   4.21   0.00 4073206     33   83.68 4744973 2123317   1347 247.32
4.72   0.00   4.21   0.00 4061118     33   80.82 4713615 2188091   1490 247.32
4.72   0.00   4.21   0.00 4051675     33   85.29 4727399 2109011   1205 247.32
4.73   0.00   4.21   0.00 4039056     33   84.65 4724735 2102603   1053 247.32

After the patch

InMpps OMpps  InGbs  OGbs err TCP Est %CPU syscalls csw     irq GBfree
5.43   0.00   4.20   0.00 3313143     33   84.96 5434214 1900162   2656 245.51
5.43   0.00   4.20   0.00 3308527     33   85.24 5439695 1809382   2521 245.51
5.42   0.00   4.19   0.00 3316778     33   87.54 5416028 1805835   2256 245.51
5.42   0.00   4.19   0.00 3317673     33   90.44 5426044 1763056   2332 245.51
5.42   0.00   4.19   0.00 3314839     33   88.11 5435732 1792218   2499 245.52
5.44   0.00   4.19   0.00 3293228     33   91.84 5426301 1668597   2121 245.52

Similarly, netperf reports 230Mb/s before the patch, and 270Mb/s after the patch

Reviewed by:	gallatin
Sponsored by:	Limelight Networks
Differential Revision:	https://reviews.freebsd.org/D15366
2018-05-18 20:13:34 +00:00
Pedro F. Giffuni
718cf2ccb9 sys/dev: further adoption of SPDX licensing ID tags.
Mainly focus on files that use BSD 2-Clause license, however the tool I
was using misidentified many licenses so this was mostly a manual - error
prone - task.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.
2017-11-27 14:52:40 +00:00
Ian Lepore
3faac3ea79 Split the hardware type enum and the hw feature flags bits into separate
fields in the softc; they're ORed together in the ofw_compat_data.

I already caught myself doing 'sc->fectype == <enum val>' without masking
out the feature bits in one place, and that's sure to happen again.
Glomming them together is convenient for storing them in the ofw_compat_data
array, but there's no reason to keep them together in the softc.
2017-10-28 20:03:29 +00:00
Ian Lepore
9aba65fa24 Use the 16-bit receive shift feature in ffec hardware that supports it.
When available, enabling this feature causes the hardware to write data
to the receive buffer starting at a 16-bit offset from the start address.
This eliminates the need to copy the data after receiving to re-align
the protocol headers to a 32-bit boundary.

PR:		222634
Submitted by:	sebastian.huber@embedded-brains.de
2017-10-28 19:34:08 +00:00
Ian Lepore
b8c7b15a82 Support up to 3 IRQs in the ffec driver.
Newer hardware splits the interrupts onto 3 different irq lines, but the
docs barely mention that there are multiple interrupts, and do not detail
how they're split up.  The code now supports 1-3 irqs, and uses the same
interrupt service routine to handle all of them.

I modified the submitted changes to use bus_alloc_resources() instead of
using loops to allocate each irq separately.  Thus, blame any bugs on me (I
can't actually test on imx7 hardware).

PR:		222634
Submitted by:	sebastian.huber@embedded-brains.de
2017-10-28 19:08:06 +00:00
Ian Lepore
21c4bbedbc Avoid AXI bus issues due to a MAC reset on imx6sx and imx7.
When the FEC is connected to the AXI bus (indicated by AVB flag), a
MAC reset while a bus transaction is pending can hang the bus.
Instead of resetting, turn off the ENABLE bit, which allows the
hardware to complete any in-progress transfers (appending a bad CRC
to any partial packet) and release the AXI bus.  This could probably
be done unconditionally for all hardware variants, but that hasn't
been tested.

PR:		222634
Submitted by:	sebastian.huber@embedded-brains.de
2017-10-28 17:30:49 +00:00
Ian Lepore
0a3df28448 Add FECFLAG_AVB variant flag to support new features on imx7.
This flag is analogous to the Linux driver FEC_QUIRK_HAS_AVB.  It
indicates an FEC with support for Audio Video Bridging (AVB).  This
indicator is used for various other parts in the Linux driver
(drivers/net/ethernet/freescale/fec_main.c).

Use it to customize the receive/transmit buffer alignment.  The receive
buffer alignment increased to 64-bytes on the i.MX 6SoloX and i.MX
7Dual.  There are no hard alignment restrictions for transmit buffers on
these chips.

Fix the ffec_softc::fectype type to provide enough storage for the
feature flags.

PR:		222634
Submitted by:	sebastian.huber@embedded-brains.de
2017-10-28 17:06:13 +00:00
Ian Lepore
a8f3fd8253 Convert from local code and constants for mac<->phy connection type to new
common fdt helper code.
2017-06-11 00:44:19 +00:00
Ian Lepore
ab3ad5bc81 if_ffec bugfixes related to harvesting of hardware-maintained statistics...
After harvesting the hardware statistics counters and summing them into the
interface stats, properly clear the hardware counters back to zero.  On imx5
and earlier hardware it is necessary to disable collection of stats while
writing zeroes to all the registers.  On imx6 and newer it turns out it's
not even possible to write zeroes, instead you have to toggle a special
"zero everything" control bit in a register.

Count incoming packets with a bad start frame delim as input errors, and
incoming packets dropped due to no fifo space as input drops.

Remove all code related to harvesting the hardware stats less often than
once per second.  It turns out the 32-bit stats registers are backed by
16-bit counters under the hood, and they can easily roll over if you only
harvest them once every 3 seconds like the old code was doing.  Now we just
read all the regs once a second.

The combination of not properly zeroing the stats registers and 16-bit
counters sometimes wrapping between harvest calls resulted in basically
unusable statistics before these changes.
2017-06-10 23:26:25 +00:00
Ian Lepore
44c63714ce Add imx6ul SoC support, and get the PHY number from the FDT data. If there
is no phy-handle property, fall back to using MII_PHY_ANY.

This still doesn't support an mdio bus with multiple PHYs on it, or the
possibility that the PHY being used by this instance of ffec is on the
mdio bus of some other instance (which is now a possibility with imx6ul).
Adding that support will require changes in fdt_get_phyaddr(), which is
currently making some assumptions that don't work with modern fdt data.
2017-04-16 03:49:14 +00:00
Ian Lepore
ad5a172c99 Fix erronious mixed use of tx/rx variables/constants in the same expression.
Pointed out by jmcneill; other instances found by grep -iE 'rx.*tx|tx.*rx'
2016-05-27 22:14:39 +00:00
Ian Lepore
e56e554106 Add busdma sync ops before reading and after modifying the descriptor rings.
This was previously working by accident because BUSDMA_COHERENT_MEMORY has
always been set to strongly-ordered on arm.  Now we're moving towards
normal-uncacheable (what might be called write-combining on other platforms)
and using the proper sync ops will be more important.  Of course, that
opens the question of just what is the "proper" sync op for shared
concurrent dma access as opposed to accesses where the handoff of control
of the memory has well-defined sequence points that match the available
busdma sync operations.
2014-11-24 16:12:11 +00:00
Gleb Smirnoff
eed9bc6a5b Mechanically convert to if_inc_counter(). 2014-09-18 20:58:04 +00:00
Gleb Smirnoff
1bffa9511f Use define from if_var.h to access a field inside struct if_data,
that resides in struct ifnet.

Sponsored by:	Nginx, Inc.
2014-08-30 19:55:54 +00:00
Hiroki Sato
b0478c2bb7 Fix another bug in multicast filtering. i.MX uses 6 bits from MSB in
LE CRC32 for the hash value, not the lowest 6 bits in BE CRC32.

Tested by:	Takanori Sawada
PR:		arm/187179
2014-03-08 14:58:39 +00:00
Hiroki Sato
cd29d6dd3b Fix multicast filtering.
Submitted by:	Takanori Sawada
PR:		arm/187179
2014-03-04 06:55:54 +00:00
Ian Lepore
add35ed5b8 Follow r261352 by updating all drivers which are children of simplebus
to check the status property in their probe routines.

Simplebus used to only instantiate its children whose status="okay"
but that was improper behavior, fixed in r261352.  Now that it doesn't
check anymore and probes all its children; the children all have to
do the check because really only the children know how to properly
interpret their status property strings.

Right now all existing drivers only understand "okay" versus something-
that's-not-okay, so they all use the new ofw_bus_status_okay() helper.
2014-02-02 19:17:28 +00:00
Ruslan Bukin
5d9306834b ENET on Vybrid Family SoC don't advertise its media capabilities
themselves properly, so force auto-negotiation.

Tested on mvf600.

Reviewed by:	ian
2014-01-04 10:19:21 +00:00
Ian Lepore
21104c7028 Switch to using ofw_bus_search_compatible() table-driven compat lookup.
Add compat strings for Freescale Vybrid family SoCs.
2013-10-26 15:15:31 +00:00
Ian Lepore
d6454cbdb5 Mask out non-address bits in the mac address register, for proper
detection of an all-zeroes address.  Also remove a misplaced return.

Reviewed by:	br@
2013-10-22 18:14:06 +00:00
Ian Lepore
dc82313758 Add a driver for the Freescale Fast Ethernet Controller found on various
Freescale SoCs including the i.MX series.  This also works for the newer
SoCs with the ENET gigabit controller, but doesn't use any of the new
hardware features other than enabling gigabit speed.
2013-10-20 21:07:38 +00:00