Commit Graph

7 Commits

Author SHA1 Message Date
Adrian Chadd
23ec80a3da Further ar71xx MII support improvements.
* Flesh out the PLL configuration fetch function, which will return the PLL
  configuration based on the unit number and speed.
* Remove the PLL speed config logic from the AR71xx/AR91xx chip PLL config
  function - pass in a 'pll' value instead.
* Modify arge_set_pll() to:
  + fetch the PLL configuration
  + write the PLL configuration
  + update the MII speed configuration.

This will allow if_arge to override the PLL configuration as required.

Obtained from:	Linux/Atheros/OpenWRT
2012-05-02 04:51:43 +00:00
Adrian Chadd
da88453012 MII related infrastructure changes.
* Add a new method to set the MII mode - GMII, RGMII, RMII, MII.
  + arge0 supports all four (two for non-Gige interfaces.)
  + arge1 only supports two (one for non-gige interfaces.)
* Set the MII clock speed when changing the MAC PLL speed.
  + Needed for AR91xx and AR71xx; not needed for AR724x.

Tested:

* AR71xx only, I'll do AR913x testing tonight and fix whichever issues
  creep up.

TODO:

* Implement the missing AR7242 arge0 PLL configuration, but don't
  adjust the MII speed accordingly.
* .. the AR7240/AR7241 don't require this, so make sure it's not set
  accidentally.

Bugs (not fixed here):

* Statically configured arge speeds are still broken - investigate why
  that is on the AP96 board.  Autonegotiate is working fine, but there
  still seems to be an occasionally heavy packet loss issue.

Obtained from: Linux/Atheros/OpenWRT
2012-05-02 01:21:57 +00:00
Adrian Chadd
0e69f431d4 Begin fleshing out MII clock rate configuration changes.
These are needed for some particular port configurations where the default
speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit
PLL rate requires a similar MII clock rate, rather than a fixed MII rate.)

This is:

* only currently implemented for the ar71xx;
* isn't used anywhere (yet), as the final interface for this hasn't yet
  been determined.
2012-03-17 07:25:23 +00:00
Aleksandr Rybalko
e319e32c90 Join chip depended methods for arge0 and arge1 into single call with unit.
Approved by: adrian (mentor)
2011-11-27 11:15:59 +00:00
Adrian Chadd
f0fb75ebd2 Tidy up the naming of the ip2 DDR flush routine, and add an inline
accessor method (which is currently unused) in there.
2011-04-29 06:25:11 +00:00
Adrian Chadd
44c5dea1d8 add the PLL set functions to cpuops 2010-08-19 16:15:30 +00:00
Adrian Chadd
4d843b15ca Bring over the first cut of the Atheros-specific SoC operations.
Each of these SoCs have different devices, different hardware initialisation
methods and, quite likely, different quirks. These functions will abstract
out the SoC differences and keep these differences out of the drivers (eg
USB init, if_arge, etc.)
2010-08-18 08:22:09 +00:00