various ports don't complain about it. It also requires that the pkg
registration bits be stick into the Xbin tarball so that they'll be
present in /usr/X11R6/lib/X11/pkgreg.tar.gz. The registration tarball
is removed upon first use to prevent it later spamming a genuine build
from ports if inadvertently extracted again.
Presumably VTOP doesn't work for static objects.
The easiest way to get it working was to reserve some space after the
environment strings and copy the bootinfo struct there.
Also, set RB_BOOTINFO, it's needed.
I got the code to load and run an unmolested kernel OK for the first time
with this system a few minutes ago - at last!. I did have to stop it
looking at the floppy though as BTX was trapping a mode 14 fault when
it look for /boot/boot.conf when no disk was in the drive. (I'm booting
from a scsi disk (bios disk 0x80)).
Now to teach it about ELF and modules :-)
o Unlock mailbox interface if we have a new card. Before only newer cards
(B or newer) that had the BIOS disabled would probe. Cards with the
BIOS enabled would fail to probe in the mailbox initialization code.
o Increase the number of ccbs and sg to 17 from 16 to support 64k I/O
on a non page aligned boundary. Ideas for dynamic determination of this
value welcomed, as more of these are better.
o Took credit for this driver, even though I derived it from Justin's code.
Made sure that Justin's copyright from bt.c was preserved, along with
his name, since the error handling code is nearly identical. Add my
own, identical copyright. Point people to aha_isa.c.
Cards tested: 1542C and 1542CF. The B and CP might work now as well,
but logistical problems precluded me from testing them this evening
(if you have jumper settings for the B card, please send me private
mail).
seen in practice. The MPspec is ambiguous and/or contradicts itself.
We now look at the ELCR to determine the trigger mode (edge/level) of an
interrupt tagged as "conforming" in the mptable. EISA interrupts appear
to be presented to the APIC as active high in all cases (they are level
inverted) that we've seen, so use this for the 'conforming' level case.
Of note, the system I'm using has 2 PCI cards in it, and the PCI cards
interrupts (5 and 9) appear in the ELCR register as level sensitive and the
mptable lists 5 and 9 as coming from the EISA bus. The PCI interrupts
are active-high by the time they reach the APIC even though they are
electrically active low at the slot.
We should still work should somebody implement this on motherboards
differently in the future as long as the mptable is clear about the
trigger/polarity.
Current should work on Holm Tiffe's machine now.
Based on code from: Tor.Egge@fast.no
