Nathan Whitehorn c8d23639da Make hard-wired TLB allocations be at minimum one page. This is required by ... some implementations, most notably (in my case) QEMU's e500 emulation.		2013-10-21 22:25:54 +00:00
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copyinout.c	Use the ABI-mandated thread pointer register (r2 for ppc32, r13 for ppc64)	2011-06-23 22:21:28 +00:00
interrupt.c	Use the ABI-mandated thread pointer register (r2 for ppc32, r13 for ppc64)	2011-06-23 22:21:28 +00:00
locore.S	1. Have the APs initialize the TLB1 entries from what has been	2012-11-03 22:02:12 +00:00
machdep_e500.c	Extract vendor specific Book-E pieces into separate files and have a common	2012-05-30 17:34:40 +00:00
machdep_ppc4xx.c	Extract vendor specific Book-E pieces into separate files and have a common	2012-05-30 17:34:40 +00:00
machdep.c	Avoid sign overflow if there are more than 2 GB of RAM.	2013-10-20 23:02:16 +00:00
mp_cpudep.c	Add SMP support on U3-based G5 systems. This does not yet work perfectly:	2009-10-23 03:17:02 +00:00
platform_bare.c	Introduce PLATFORMMETHOD_END and use it.	2013-02-13 02:21:45 +00:00
pmap.c	Make hard-wired TLB allocations be at minimum one page. This is required by	2013-10-21 22:25:54 +00:00
swtch.S	MFppc64:	2010-07-13 05:32:19 +00:00
trap_subr.S	Fix a typo that resulted in or-ing PTE_UW twice whrn PTE_SW was needed.	2012-07-02 21:21:12 +00:00
trap.c	userret() already checks for td_locks when INVARIANTS is enabled, so	2012-09-08 18:27:11 +00:00