122 lines
4.9 KiB
C
122 lines
4.9 KiB
C
/*-
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* Copyright (c) 1993 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_IPL_H_
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#define _MACHINE_IPL_H_
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#ifdef APIC_IO
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#include <i386/isa/apic_ipl.h>
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#else
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#include <i386/isa/icu_ipl.h>
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#endif
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/*
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* Software interrupt bit numbers in priority order. The priority only
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* determines which swi will be dispatched next; a higher priority swi
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* may be dispatched when a nested h/w interrupt handler returns.
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*/
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#define SWI_TTY (NHWI + 0)
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#define SWI_NET (NHWI + 1)
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#define SWI_CAMNET (NHWI + 2)
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#define SWI_CAMBIO (NHWI + 3)
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#define SWI_VM (NHWI + 4)
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#define SWI_TQ (NHWI + 5)
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#define SWI_CLOCK (NHWI + 6)
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#define NSWI 7
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/*
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* Corresponding interrupt-pending bits for ipending.
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*/
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#define SWI_TTY_PENDING (1 << SWI_TTY)
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#define SWI_NET_PENDING (1 << SWI_NET)
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#define SWI_CAMNET_PENDING (1 << SWI_CAMNET)
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#define SWI_CAMBIO_PENDING (1 << SWI_CAMBIO)
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#define SWI_VM_PENDING (1 << SWI_VM)
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#define SWI_TQ_PENDING (1 << SWI_TQ)
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#define SWI_CLOCK_PENDING (1 << SWI_CLOCK)
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/*
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* Corresponding interrupt-disable masks for cpl. The ordering is now by
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* inclusion (where each mask is considered as a set of bits). Everything
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* except SWI_CLOCK_MASK includes SWI_LOW_MASK so that softclock() and low
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* priority swi's don't run while other swi handlers are running and timeout
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* routines can call swi handlers. SWI_TTY_MASK includes SWI_NET_MASK in
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* case tty interrupts are processed at splsofttty() for a tty that is in
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* SLIP or PPP line discipline (this is weaker than merging net_imask with
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* tty_imask in isa.c - splimp() must mask hard and soft tty interrupts, but
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* spltty() apparently only needs to mask soft net interrupts).
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*/
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#define SWI_TTY_MASK (SWI_TTY_PENDING | SWI_LOW_MASK | SWI_NET_MASK)
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#define SWI_CAMNET_MASK (SWI_CAMNET_PENDING | SWI_LOW_MASK)
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#define SWI_CAMBIO_MASK (SWI_CAMBIO_PENDING | SWI_LOW_MASK)
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#define SWI_NET_MASK (SWI_NET_PENDING | SWI_LOW_MASK)
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#define SWI_VM_MASK (SWI_VM_PENDING | SWI_LOW_MASK)
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#define SWI_TQ_MASK (SWI_TQ_PENDING | SWI_LOW_MASK)
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#define SWI_CLOCK_MASK SWI_CLOCK_PENDING
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#define SWI_LOW_MASK (SWI_TQ_PENDING | SWI_CLOCK_MASK)
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#define SWI_MASK (~HWI_MASK)
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/*
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* astpending bits
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*/
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#define AST_PENDING 0x00000001
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#define AST_RESCHED 0x00000002
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#ifndef LOCORE
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/*
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* cpl is preserved by interrupt handlers so it is effectively nonvolatile.
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* ipending and idelayed are changed by interrupt handlers so they are
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* volatile.
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*/
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#ifdef notyet /* in <sys/interrupt.h> until pci drivers stop hacking on them */
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extern unsigned bio_imask; /* group of interrupts masked with splbio() */
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#endif
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extern unsigned cpl; /* current priority level mask */
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#ifdef SMP
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extern unsigned cil; /* current INTerrupt level mask */
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#endif
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extern volatile unsigned idelayed; /* interrupts to become pending */
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extern volatile unsigned ipending; /* active interrupts masked by cpl */
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#ifdef notyet /* in <sys/systm.h> until pci drivers stop hacking on them */
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extern unsigned net_imask; /* group of interrupts masked with splimp() */
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extern unsigned stat_imask; /* interrupts masked with splstatclock() */
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extern unsigned tty_imask; /* group of interrupts masked with spltty() */
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#endif
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#endif /* !LOCORE */
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#endif /* !_MACHINE_IPL_H_ */
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