1b86b1d21a
This just requires a little HAL change (add a new config parameter) and some glue in if_ath_pci.c, however I'm leaving this up for someone else to do. Obtained from: Qualcomm Atheros
545 lines
16 KiB
C
545 lines
16 KiB
C
/*
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* Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
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* Copyright (c) 2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_devid.h"
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#include "ah_eeprom_v4k.h" /* XXX for tx/rx gain */
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#include "ar9002/ar9280.h"
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#include "ar9002/ar9285.h"
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#include "ar5416/ar5416reg.h"
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#include "ar5416/ar5416phy.h"
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#include "ar9002/ar9285.ini"
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#include "ar9002/ar9285v2.ini"
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#include "ar9002/ar9280v2.ini" /* XXX ini for tx/rx gain */
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#include "ar9002/ar9285_cal.h"
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#include "ar9002/ar9285_phy.h"
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#include "ar9002/ar9285_diversity.h"
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static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
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.calName = "IQ", .calType = IQ_MISMATCH_CAL,
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.calNumSamples = MIN_CAL_SAMPLES,
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.calCountMax = PER_MAX_LOG_COUNT,
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.calCollect = ar5416IQCalCollect,
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.calPostProc = ar5416IQCalibration
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};
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static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */
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.calName = "ADC Gain", .calType = ADC_GAIN_CAL,
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.calNumSamples = MIN_CAL_SAMPLES,
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.calCountMax = PER_MIN_LOG_COUNT,
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.calCollect = ar5416AdcGainCalCollect,
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.calPostProc = ar5416AdcGainCalibration
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};
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static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */
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.calName = "ADC DC", .calType = ADC_DC_CAL,
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.calNumSamples = MIN_CAL_SAMPLES,
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.calCountMax = PER_MIN_LOG_COUNT,
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.calCollect = ar5416AdcDcCalCollect,
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.calPostProc = ar5416AdcDcCalibration
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};
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static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = {
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.calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
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.calNumSamples = MIN_CAL_SAMPLES,
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.calCountMax = INIT_LOG_COUNT,
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.calCollect = ar5416AdcDcCalCollect,
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.calPostProc = ar5416AdcDcCalibration
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};
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static void ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
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HAL_BOOL power_off);
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static void ar9285DisablePCIE(struct ath_hal *ah);
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static HAL_BOOL ar9285FillCapabilityInfo(struct ath_hal *ah);
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static void ar9285WriteIni(struct ath_hal *ah,
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const struct ieee80211_channel *chan);
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static void
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ar9285AniSetup(struct ath_hal *ah)
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{
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/*
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* These are the parameters from the AR5416 ANI code;
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* they likely need quite a bit of adjustment for the
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* AR9285.
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*/
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static const struct ar5212AniParams aniparams = {
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.maxNoiseImmunityLevel = 4, /* levels 0..4 */
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.totalSizeDesired = { -55, -55, -55, -55, -62 },
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.coarseHigh = { -14, -14, -14, -14, -12 },
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.coarseLow = { -64, -64, -64, -64, -70 },
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.firpwr = { -78, -78, -78, -78, -80 },
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.maxSpurImmunityLevel = 2,
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.cycPwrThr1 = { 2, 4, 6 },
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.maxFirstepLevel = 2, /* levels 0..2 */
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.firstep = { 0, 4, 8 },
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.ofdmTrigHigh = 500,
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.ofdmTrigLow = 200,
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.cckTrigHigh = 200,
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.cckTrigLow = 100,
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.rssiThrHigh = 40,
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.rssiThrLow = 7,
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.period = 100,
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};
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/* NB: disable ANI noise immmunity for reliable RIFS rx */
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AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);
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ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
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}
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/*
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* Attach for an AR9285 part.
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*/
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static struct ath_hal *
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ar9285Attach(uint16_t devid, HAL_SOFTC sc,
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HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
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HAL_STATUS *status)
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{
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struct ath_hal_9285 *ahp9285;
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struct ath_hal_5212 *ahp;
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struct ath_hal *ah;
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uint32_t val;
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HAL_STATUS ecode;
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HAL_BOOL rfStatus;
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HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
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__func__, sc, (void*) st, (void*) sh);
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/* NB: memory is returned zero'd */
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ahp9285 = ath_hal_malloc(sizeof (struct ath_hal_9285));
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if (ahp9285 == AH_NULL) {
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HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
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"%s: cannot allocate memory for state block\n", __func__);
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*status = HAL_ENOMEM;
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return AH_NULL;
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}
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ahp = AH5212(ahp9285);
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ah = &ahp->ah_priv.h;
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ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
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/*
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* Use the "local" EEPROM data given to us by the higher layers.
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* This is a private copy out of system flash. The Linux ath9k
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* commit for the initial AR9130 support mentions MMIO flash
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* access is "unreliable." -adrian
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*/
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if (eepromdata != AH_NULL) {
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AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;
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AH_PRIVATE(ah)->ah_eepromWrite = NULL;
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ah->ah_eepromdata = eepromdata;
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}
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/* XXX override with 9285 specific state */
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/* override 5416 methods for our needs */
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AH5416(ah)->ah_initPLL = ar9280InitPLL;
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ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch;
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ah->ah_configPCIE = ar9285ConfigPCIE;
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ah->ah_disablePCIE = ar9285DisablePCIE;
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ah->ah_setTxPower = ar9285SetTransmitPower;
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ah->ah_setBoardValues = ar9285SetBoardValues;
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AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
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AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
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AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
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AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
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AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
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AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
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AH5416(ah)->ah_writeIni = ar9285WriteIni;
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AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
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AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
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ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD >> 1;
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if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
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/* reset chip */
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
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__func__);
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ecode = HAL_EIO;
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goto bad;
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}
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if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
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__func__);
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ecode = HAL_EIO;
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goto bad;
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}
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/* Read Revisions from Chips before taking out of reset */
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val = OS_REG_READ(ah, AR_SREV);
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HALDEBUG(ah, HAL_DEBUG_ATTACH,
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"%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
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__func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
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MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
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/* NB: include chip type to differentiate from pre-Sowl versions */
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AH_PRIVATE(ah)->ah_macVersion =
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(val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
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AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
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AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
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/* setup common ini data; rf backends handle remainder */
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if (AR_SREV_KITE_12_OR_LATER(ah)) {
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HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6);
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HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2);
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HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
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ar9285PciePhy_clkreq_always_on_L1_v2, 2);
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} else {
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HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6);
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HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2);
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HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
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ar9285PciePhy_clkreq_always_on_L1, 2);
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}
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ar5416AttachPCIE(ah);
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/* Attach methods that require MAC version/revision info */
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if (AR_SREV_KITE_12_OR_LATER(ah))
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AH5416(ah)->ah_cal_initcal = ar9285InitCalHardware;
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if (AR_SREV_KITE_11_OR_LATER(ah))
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AH5416(ah)->ah_cal_pacal = ar9002_hw_pa_cal;
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ecode = ath_hal_v4kEepromAttach(ah);
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if (ecode != HAL_OK)
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goto bad;
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if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
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__func__);
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ecode = HAL_EIO;
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goto bad;
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}
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AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
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if (!ar5212ChipTest(ah)) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
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__func__);
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ecode = HAL_ESELFTEST;
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goto bad;
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}
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/*
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* Set correct Baseband to analog shift
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* setting to access analog chips.
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*/
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OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
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/* Read Radio Chip Rev Extract */
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AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
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switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
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case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
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case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
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break;
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default:
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if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
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AH_PRIVATE(ah)->ah_analog5GhzRev =
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AR_RAD5133_SREV_MAJOR;
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break;
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}
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#ifdef AH_DEBUG
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: 5G Radio Chip Rev 0x%02X is not supported by "
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"this driver\n", __func__,
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AH_PRIVATE(ah)->ah_analog5GhzRev);
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ecode = HAL_ENOTSUPP;
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goto bad;
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#endif
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}
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rfStatus = ar9285RfAttach(ah, &ecode);
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if (!rfStatus) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
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__func__, ecode);
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goto bad;
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}
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HAL_INI_INIT(&ahp9285->ah_ini_rxgain, ar9280Modes_original_rxgain_v2,
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6);
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if (AR_SREV_9285E_20(ah))
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ath_hal_printf(ah, "[ath] AR9285E_20 detected; using XE TX gain tables\n");
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/* setup txgain table */
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switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
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case AR5416_EEP_TXGAIN_HIGH_POWER:
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if (AR_SREV_9285E_20(ah))
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HAL_INI_INIT(&ahp9285->ah_ini_txgain,
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ar9285Modes_XE2_0_high_power, 6);
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else
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HAL_INI_INIT(&ahp9285->ah_ini_txgain,
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ar9285Modes_high_power_tx_gain_v2, 6);
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break;
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case AR5416_EEP_TXGAIN_ORIG:
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if (AR_SREV_9285E_20(ah))
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HAL_INI_INIT(&ahp9285->ah_ini_txgain,
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ar9285Modes_XE2_0_normal_power, 6);
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else
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HAL_INI_INIT(&ahp9285->ah_ini_txgain,
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ar9285Modes_original_tx_gain_v2, 6);
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break;
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default:
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HALASSERT(AH_FALSE);
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goto bad; /* XXX ? try to continue */
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}
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/*
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* Got everything we need now to setup the capabilities.
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*/
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if (!ar9285FillCapabilityInfo(ah)) {
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ecode = HAL_EEREAD;
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goto bad;
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}
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/* Print out whether the EEPROM settings enable AR9285 diversity */
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if (ar9285_check_div_comb(ah)) {
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ath_hal_printf(ah, "[ath] Enabling diversity for Kite\n");
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ah->ah_rxAntCombDiversity = ar9285_ant_comb_scan;
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}
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/* Disable 11n for the AR2427 */
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if (devid == AR2427_DEVID_PCIE)
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AH_PRIVATE(ah)->ah_caps.halHTSupport = AH_FALSE;
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ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
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if (ecode != HAL_OK) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: error getting mac address from EEPROM\n", __func__);
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goto bad;
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}
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/* XXX How about the serial number ? */
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/* Read Reg Domain */
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AH_PRIVATE(ah)->ah_currentRD =
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ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
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/*
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* For Kite and later chipsets, the following bits are not
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* programmed in EEPROM and so are set as enabled always.
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*/
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AH_PRIVATE(ah)->ah_currentRDext = AR9285_RDEXT_DEFAULT;
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/*
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* ah_miscMode is populated by ar5416FillCapabilityInfo()
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* starting from griffin. Set here to make sure that
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* AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
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* placed into hardware.
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*/
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if (ahp->ah_miscMode != 0)
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OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
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ar9285AniSetup(ah); /* Anti Noise Immunity */
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/* Setup noise floor min/max/nominal values */
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AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
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AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
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AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
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/* XXX no 5ghz values? */
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ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
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HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
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return ah;
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bad:
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if (ah != AH_NULL)
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ah->ah_detach(ah);
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if (status)
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*status = ecode;
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return AH_NULL;
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}
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static void
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ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
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{
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uint32_t val;
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/*
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* This workaround needs some integration work with the HAL
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* config parameters and the if_ath_pci.c glue.
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* Specifically, read the value of the PCI register 0x70c
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* (4 byte PCI config space register) and store it in ath_hal_war70c.
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* Then if it's non-zero, the below WAR would override register
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* 0x570c upon suspend/resume.
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*/
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#if 0
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if (AR_SREV_9285E_20(ah)) {
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val = AH_PRIVATE(ah)->ah_config.ath_hal_war70c;
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if (val) {
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val &= 0xffff00ff;
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val |= 0x6f00;
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OS_REG_WRITE(ah, 0x570c, val);
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}
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}
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#endif
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if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
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ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
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OS_DELAY(1000);
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}
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/*
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* Set PCIe workaround bits
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*
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* NOTE:
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*
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* In Merlin and Kite, bit 14 in WA register (disable L1) should only
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* be set when device enters D3 and be cleared when device comes back
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* to D0.
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*/
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if (power_off) { /* Power-off */
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OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
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val = OS_REG_READ(ah, AR_WA);
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/*
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* Disable bit 6 and 7 before entering D3 to prevent
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* system hang.
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*/
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val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
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/*
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* See above: set AR_WA_D3_L1_DISABLE when entering D3 state.
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*
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* XXX The reference HAL does it this way - it only sets
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* AR_WA_D3_L1_DISABLE if it's set in AR9280_WA_DEFAULT,
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* which it (currently) isn't. So the following statement
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* is currently a NOP.
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*/
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if (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)
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val |= AR_WA_D3_L1_DISABLE;
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if (AR_SREV_9285E_20(ah))
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val |= AR_WA_BIT23;
|
|
|
|
OS_REG_WRITE(ah, AR_WA, val);
|
|
} else { /* Power-on */
|
|
val = AR9285_WA_DEFAULT;
|
|
/*
|
|
* See note above: make sure L1_DISABLE is not set.
|
|
*/
|
|
val &= (~AR_WA_D3_L1_DISABLE);
|
|
|
|
/* Software workaroud for ASPM system hang. */
|
|
val |= (AR_WA_BIT6 | AR_WA_BIT7);
|
|
|
|
if (AR_SREV_9285E_20(ah))
|
|
val |= AR_WA_BIT23;
|
|
|
|
OS_REG_WRITE(ah, AR_WA, val);
|
|
|
|
/* set bit 19 to allow forcing of pcie core into L1 state */
|
|
OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
|
|
}
|
|
}
|
|
|
|
static void
|
|
ar9285DisablePCIE(struct ath_hal *ah)
|
|
{
|
|
}
|
|
|
|
static void
|
|
ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
|
{
|
|
u_int modesIndex, freqIndex;
|
|
int regWrites = 0;
|
|
|
|
/* Setup the indices for the next set of register array writes */
|
|
/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
|
|
freqIndex = 2;
|
|
if (IEEE80211_IS_CHAN_HT40(chan))
|
|
modesIndex = 3;
|
|
else if (IEEE80211_IS_CHAN_108G(chan))
|
|
modesIndex = 5;
|
|
else
|
|
modesIndex = 4;
|
|
|
|
/* Set correct Baseband to analog shift setting to access analog chips. */
|
|
OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
|
|
OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
|
|
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
|
|
modesIndex, regWrites);
|
|
if (AR_SREV_KITE_12_OR_LATER(ah)) {
|
|
regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,
|
|
modesIndex, regWrites);
|
|
}
|
|
regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
|
|
1, regWrites);
|
|
}
|
|
|
|
/*
|
|
* Fill all software cached or static hardware state information.
|
|
* Return failure if capabilities are to come from EEPROM and
|
|
* cannot be read.
|
|
*/
|
|
static HAL_BOOL
|
|
ar9285FillCapabilityInfo(struct ath_hal *ah)
|
|
{
|
|
HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
|
|
|
|
if (!ar5416FillCapabilityInfo(ah))
|
|
return AH_FALSE;
|
|
pCap->halNumGpioPins = 12;
|
|
pCap->halWowSupport = AH_TRUE;
|
|
pCap->halWowMatchPatternExact = AH_TRUE;
|
|
#if 0
|
|
pCap->halWowMatchPatternDword = AH_TRUE;
|
|
#endif
|
|
/* AR9285 has 2 antennas but is a 1x1 stream device */
|
|
pCap->halTxStreams = 1;
|
|
pCap->halRxStreams = 1;
|
|
|
|
pCap->halCSTSupport = AH_TRUE;
|
|
pCap->halRifsRxSupport = AH_TRUE;
|
|
pCap->halRifsTxSupport = AH_TRUE;
|
|
pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
|
|
pCap->halExtChanDfsSupport = AH_TRUE;
|
|
pCap->halUseCombinedRadarRssi = AH_TRUE;
|
|
#if 0
|
|
/* XXX bluetooth */
|
|
pCap->halBtCoexSupport = AH_TRUE;
|
|
#endif
|
|
pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
|
|
pCap->hal4kbSplitTransSupport = AH_FALSE;
|
|
/* Disable this so Block-ACK works correctly */
|
|
pCap->halHasRxSelfLinkedTail = AH_FALSE;
|
|
pCap->halMbssidAggrSupport = AH_TRUE;
|
|
pCap->hal4AddrAggrSupport = AH_TRUE;
|
|
|
|
if (AR_SREV_KITE_12_OR_LATER(ah))
|
|
pCap->halPSPollBroken = AH_FALSE;
|
|
|
|
/* Only RX STBC supported */
|
|
pCap->halRxStbcSupport = 1;
|
|
pCap->halTxStbcSupport = 0;
|
|
|
|
return AH_TRUE;
|
|
}
|
|
|
|
static const char*
|
|
ar9285Probe(uint16_t vendorid, uint16_t devid)
|
|
{
|
|
if (vendorid == ATHEROS_VENDOR_ID && devid == AR9285_DEVID_PCIE)
|
|
return "Atheros 9285";
|
|
if (vendorid == ATHEROS_VENDOR_ID && (devid == AR2427_DEVID_PCIE))
|
|
return "Atheros 2427";
|
|
|
|
return AH_NULL;
|
|
}
|
|
AH_CHIP(AR9285, ar9285Probe, ar9285Attach);
|