0d356a5349
OPAL unconditionally enters secondary CPUs with only HV and SF set. I tried writing a secondary entry point instead, but OPAL rejected it and I am unsure why, so I resorted to making the system reset interrupt endian-flexible. This means we take a slight performance hit on wakeup on LE, but it is a good stopgap until we can figure out a reliable way to make OPAL enter where we want it to. It probably makes sense to have it around anyway, because I can imagine scenarios where the cpu resets itself to BE and does a software reset. Sponsored by: Tag1 Consulting, Inc. |
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aim | ||
amigaone | ||
booke | ||
conf | ||
cpufreq | ||
fpu | ||
include | ||
mambo | ||
mikrotik | ||
mpc85xx | ||
ofw | ||
powermac | ||
powernv | ||
powerpc | ||
ps3 | ||
pseries | ||
psim |