Michal Meloun a89156f53f ARM: Use new ARMv6 naming conventions for cache and TLB functions ... in all but ARMv4 specific files. Expand ARMv6 compatibility stubs in cpu-v4.h. Use physical address in L2 cache functions if ARM_L2_PIPT is defined.		2016-02-05 14:57:41 +00:00
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armada38x_mp.c	Introduce initial driver for PMSU on Armada38x	2016-01-20 14:49:16 +00:00
armada38x.c	Open window to bootROM memory on Armada38x to allow CPU1 to boot	2016-01-20 14:30:17 +00:00
files.armada38x	Introduce initial driver for PMSU on Armada38x	2016-01-20 14:49:16 +00:00
pmsu.c	ARM: Use new ARMv6 naming conventions for cache and TLB functions	2016-02-05 14:57:41 +00:00
pmsu.h	Introduce initial driver for PMSU on Armada38x	2016-01-20 14:49:16 +00:00
rtc.c	Add a new RTC driver for Armada38x	2016-01-20 14:18:49 +00:00
std.armada38x	Add initial support for SMP on Armada38x	2016-01-20 14:45:54 +00:00