7a22215c53
shifts into the sign bit. Instead use (1U << 31) which gets the expected result. This fix is not ideal as it assumes a 32 bit int, but does fix the issue for most cases. A similar change was made in OpenBSD. Discussed with: -arch, rdivacky Reviewed by: cperciva
102 lines
3.8 KiB
C
102 lines
3.8 KiB
C
/*-
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* Copyright (c) 2012, 2013 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Oleksandr Rybalko under sponsorship
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* from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* Registers definition for Freescale i.MX515 Generic Periodic Timer */
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#define IMX_GPT_CR 0x0000 /* Control Register R/W */
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#define GPT_CR_FO3 (1U << 31)
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#define GPT_CR_FO2 (1 << 30)
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#define GPT_CR_FO1 (1 << 29)
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#define GPT_CR_OM3_SHIFT 26
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#define GPT_CR_OM3_MASK 0x1c000000
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#define GPT_CR_OM2_SHIFT 23
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#define GPT_CR_OM2_MASK 0x03800000
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#define GPT_CR_OM1_SHIFT 20
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#define GPT_CR_OM1_MASK 0x00700000
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#define GPT_CR_OMX_NONE 0
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#define GPT_CR_OMX_TOGGLE 1
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#define GPT_CR_OMX_CLEAR 2
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#define GPT_CR_OMX_SET 3
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#define GPT_CR_OMX_PULSE 4 /* Run CLKSRC on output pin */
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#define GPT_CR_IM2_SHIFT 18
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#define GPT_CR_IM2_MASK 0x000c0000
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#define GPT_CR_IM1_SHIFT 16
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#define GPT_CR_IM1_MASK 0x00030000
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#define GPT_CR_IMX_NONE 0
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#define GPT_CR_IMX_REDGE 1
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#define GPT_CR_IMX_FEDGE 2
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#define GPT_CR_IMX_BOTH 3
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#define GPT_CR_SWR (1 << 15)
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#define GPT_CR_24MEN (1 << 10)
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#define GPT_CR_FRR (1 << 9)
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#define GPT_CR_CLKSRC_NONE (0 << 6)
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#define GPT_CR_CLKSRC_IPG (1 << 6)
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#define GPT_CR_CLKSRC_IPG_HIGH (2 << 6)
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#define GPT_CR_CLKSRC_EXT (3 << 6)
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#define GPT_CR_CLKSRC_32K (4 << 6)
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#define GPT_CR_CLKSRC_24M (5 << 6)
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#define GPT_CR_STOPEN (1 << 5)
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#define GPT_CR_DOZEEN (1 << 4)
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#define GPT_CR_WAITEN (1 << 3)
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#define GPT_CR_DBGEN (1 << 2)
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#define GPT_CR_ENMOD (1 << 1)
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#define GPT_CR_EN (1 << 0)
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#define IMX_GPT_PR 0x0004 /* Prescaler Register R/W */
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#define GPT_PR_VALUE_SHIFT 0
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#define GPT_PR_VALUE_MASK 0x00000fff
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#define GPT_PR_VALUE_SHIFT_24M 12
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#define GPT_PR_VALUE_MASK_24M 0x0000f000
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/* Same map for SR and IR */
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#define IMX_GPT_SR 0x0008 /* Status Register R/W */
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#define IMX_GPT_IR 0x000c /* Interrupt Register R/W */
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#define GPT_IR_ROV (1 << 5)
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#define GPT_IR_IF2 (1 << 4)
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#define GPT_IR_IF1 (1 << 3)
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#define GPT_IR_OF3 (1 << 2)
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#define GPT_IR_OF2 (1 << 1)
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#define GPT_IR_OF1 (1 << 0)
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#define GPT_IR_ALL \
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(GPT_IR_ROV | \
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GPT_IR_IF2 | \
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GPT_IR_IF1 | \
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GPT_IR_OF3 | \
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GPT_IR_OF2 | \
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GPT_IR_OF1)
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#define IMX_GPT_OCR1 0x0010 /* Output Compare Register 1 R/W */
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#define IMX_GPT_OCR2 0x0014 /* Output Compare Register 2 R/W */
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#define IMX_GPT_OCR3 0x0018 /* Output Compare Register 3 R/W */
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#define IMX_GPT_ICR1 0x001c /* Input capture Register 1 RO */
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#define IMX_GPT_ICR2 0x0020 /* Input capture Register 2 RO */
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#define IMX_GPT_CNT 0x0024 /* Counter Register RO */
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