Conrad Meyer 16068ae479 Add definitions for AMD Spectre/Meltdown CPUID information ... No functional change, aside from printing recognized bits in CPU identification. The bits are documented in 111006-B "Indirect Branch Control Extension"[1] and 124441 "Speculative Store Bypass Disable."[2] Notably missing (left as future work): * Integration with hw.spec_store_bypass_disable and hw_ssb_active flag, which are currently Intel-specific * Integration with hw_ibrs_active global flag, which are currently Intel-specific * SSB_NO integration in hw_ssb_recalculate() * Bhyve integration (PR 235010) [1]: https://developer.amd.com/wp-content/resources/111006-B_AMD64TechnologyIndirectBranchControlExtenstion_WP_7-18Update_FNL.pdf [2]: https://developer.amd.com/wp-content/resources/124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf PR: 235010 (related, but does not fix) MFC after: a week		2019-01-17 19:44:47 +00:00
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acpica	acpica : move SRAT/SLIT parsing to sys/dev/acpica	2018-12-08 19:10:58 +00:00
bios	sys/x86: further adoption of SPDX licensing ID tags.	2017-11-27 15:11:47 +00:00
cpufreq	cpufreq: Remove error-prone table terminators in favor of automatic sizing	2018-04-14 03:15:05 +00:00
include	Add definitions for AMD Spectre/Meltdown CPUID information	2019-01-17 19:44:47 +00:00
iommu	Add malloc_domainset(9) and _domainset variants to other allocator KPIs.	2018-10-30 18:26:34 +00:00
isa	Fix a regression in r338360 when booting an x86 machine without APIC.	2018-09-17 17:18:54 +00:00
pci	Add pci_early function to detect Intel stolen memory.	2018-10-31 23:17:00 +00:00
x86	Add definitions for AMD Spectre/Meltdown CPUID information	2019-01-17 19:44:47 +00:00
xen	Correct variable name in two panic messages: num_msi_irq -> num_msi_irqs.	2018-12-31 22:46:43 +00:00