09728b2df6
The SiFive FU540 Power Reset Clocking Interrupt block contains a PLL that turns the input crystal (33.3MHz) into a 1-1.5GHz clock. This clock in turn is divided by two to produce the tlclk, which is fed into devices such as the SPI and I2C controllers. Register a new clock device for the PRCI so that those devices can read the correct clock through the clk framework. Submitted by: kp Sponsored by: Axiado
4 lines
45 B
Plaintext
4 lines
45 B
Plaintext
# $FreeBSD$
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files "../sifive/files.sifive"
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