3de0952fba
Submitted by: pkanneganti@cavium.com (Prasad V Kanneganti) MFC after: 1 week Sponsored by: Cavium Networks Differential Revision: https://reviews.freebsd.org/D12415
277 lines
7.0 KiB
C
277 lines
7.0 KiB
C
/*
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* BSD LICENSE
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*
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* Copyright(c) 2017 Cavium, Inc.. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Cavium, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*$FreeBSD$*/
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#include "lio_bsd.h"
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#include "lio_common.h"
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#include "lio_droq.h"
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#include "lio_iq.h"
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#include "lio_response_manager.h"
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#include "lio_device.h"
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#include "lio_mem_ops.h"
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#define MEMOPS_IDX LIO_MAX_BAR1_MAP_INDEX
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#if BYTE_ORDER == BIG_ENDIAN
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static inline void
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lio_toggle_bar1_swapmode(struct octeon_device *oct, uint32_t idx)
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{
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uint32_t mask;
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mask = oct->fn_list.bar1_idx_read(oct, idx);
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mask = (mask & 0x2) ? (mask & ~2) : (mask | 2);
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oct->fn_list.bar1_idx_write(oct, idx, mask);
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}
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#else /* BYTE_ORDER != BIG_ENDIAN */
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#define lio_toggle_bar1_swapmode(oct, idx)
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#endif /* BYTE_ORDER == BIG_ENDIAN */
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static inline void
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lio_write_bar1_mem8(struct octeon_device *oct, uint32_t reg, uint64_t val)
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{
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bus_space_write_1(oct->mem_bus_space[1].tag,
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oct->mem_bus_space[1].handle, reg, val);
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}
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#ifdef __i386__
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static inline uint32_t
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lio_read_bar1_mem32(struct octeon_device *oct, uint32_t reg)
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{
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return (bus_space_read_4(oct->mem_bus_space[1].tag,
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oct->mem_bus_space[1].handle, reg));
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}
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static inline void
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lio_write_bar1_mem32(struct octeon_device *oct, uint32_t reg, uint32_t val)
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{
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bus_space_write_4(oct->mem_bus_space[1].tag,
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oct->mem_bus_space[1].handle, reg, val);
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}
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#endif
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static inline uint64_t
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lio_read_bar1_mem64(struct octeon_device *oct, uint32_t reg)
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{
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#ifdef __i386__
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return (lio_read_bar1_mem32(oct, reg) |
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((uint64_t)lio_read_bar1_mem32(oct, reg + 4) << 32));
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#else
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return (bus_space_read_8(oct->mem_bus_space[1].tag,
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oct->mem_bus_space[1].handle, reg));
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#endif
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}
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static inline void
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lio_write_bar1_mem64(struct octeon_device *oct, uint32_t reg, uint64_t val)
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{
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#ifdef __i386__
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lio_write_bar1_mem32(oct, reg, (uint32_t)val);
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lio_write_bar1_mem32(oct, reg + 4, val >> 32);
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#else
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bus_space_write_8(oct->mem_bus_space[1].tag,
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oct->mem_bus_space[1].handle, reg, val);
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#endif
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}
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static void
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lio_pci_fastwrite(struct octeon_device *oct, uint32_t offset,
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uint8_t *hostbuf, uint32_t len)
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{
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while ((len) && ((unsigned long)offset) & 7) {
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lio_write_bar1_mem8(oct, offset++, *(hostbuf++));
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len--;
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}
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lio_toggle_bar1_swapmode(oct, MEMOPS_IDX);
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while (len >= 8) {
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lio_write_bar1_mem64(oct, offset, *((uint64_t *)hostbuf));
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offset += 8;
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hostbuf += 8;
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len -= 8;
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}
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lio_toggle_bar1_swapmode(oct, MEMOPS_IDX);
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while (len--)
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lio_write_bar1_mem8(oct, offset++, *(hostbuf++));
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}
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static inline uint64_t
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lio_read_bar1_mem8(struct octeon_device *oct, uint32_t reg)
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{
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return (bus_space_read_1(oct->mem_bus_space[1].tag,
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oct->mem_bus_space[1].handle, reg));
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}
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static void
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lio_pci_fastread(struct octeon_device *oct, uint32_t offset,
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uint8_t *hostbuf, uint32_t len)
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{
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while ((len) && ((unsigned long)offset) & 7) {
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*(hostbuf++) = lio_read_bar1_mem8(oct, offset++);
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len--;
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}
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lio_toggle_bar1_swapmode(oct, MEMOPS_IDX);
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while (len >= 8) {
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*((uint64_t *)hostbuf) = lio_read_bar1_mem64(oct, offset);
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offset += 8;
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hostbuf += 8;
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len -= 8;
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}
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lio_toggle_bar1_swapmode(oct, MEMOPS_IDX);
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while (len--)
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*(hostbuf++) = lio_read_bar1_mem8(oct, offset++);
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}
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/* Core mem read/write with temporary bar1 settings. */
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/* op = 1 to read, op = 0 to write. */
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static void
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lio_pci_rw_core_mem(struct octeon_device *oct, uint64_t addr,
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uint8_t *hostbuf, uint32_t len, uint32_t op)
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{
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uint64_t static_mapping_base;
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uint32_t copy_len = 0, index_reg_val = 0;
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uint32_t offset;
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static_mapping_base = oct->console_nb_info.dram_region_base;
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if (static_mapping_base && static_mapping_base ==
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(addr & 0xFFFFFFFFFFC00000ULL)) {
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int bar1_index = oct->console_nb_info.bar1_index;
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offset = (bar1_index << 22) + (addr & 0x3fffff);
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if (op)
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lio_pci_fastread(oct, offset, hostbuf, len);
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else
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lio_pci_fastwrite(oct, offset, hostbuf, len);
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return;
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}
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mtx_lock(&oct->mem_access_lock);
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/* Save the original index reg value. */
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index_reg_val = oct->fn_list.bar1_idx_read(oct, MEMOPS_IDX);
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do {
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oct->fn_list.bar1_idx_setup(oct, addr, MEMOPS_IDX, 1);
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offset = (MEMOPS_IDX << 22) + (addr & 0x3fffff);
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/*
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* If operation crosses a 4MB boundary, split the transfer
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* at the 4MB boundary.
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*/
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if (((addr + len - 1) & ~(0x3fffff)) != (addr & ~(0x3fffff))) {
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copy_len = (uint32_t)(((addr & ~(0x3fffff)) +
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(MEMOPS_IDX << 22)) - addr);
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} else {
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copy_len = len;
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}
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if (op) { /* read from core */
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lio_pci_fastread(oct, offset, hostbuf,
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copy_len);
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} else {
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lio_pci_fastwrite(oct, offset, hostbuf,
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copy_len);
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}
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len -= copy_len;
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addr += copy_len;
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hostbuf += copy_len;
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} while (len);
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oct->fn_list.bar1_idx_write(oct, MEMOPS_IDX, index_reg_val);
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mtx_unlock(&oct->mem_access_lock);
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}
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void
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lio_pci_read_core_mem(struct octeon_device *oct, uint64_t coreaddr,
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uint8_t *buf, uint32_t len)
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{
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lio_pci_rw_core_mem(oct, coreaddr, buf, len, 1);
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}
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void
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lio_pci_write_core_mem(struct octeon_device *oct, uint64_t coreaddr,
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uint8_t *buf, uint32_t len)
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{
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lio_pci_rw_core_mem(oct, coreaddr, buf, len, 0);
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}
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uint64_t
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lio_read_device_mem64(struct octeon_device *oct, uint64_t coreaddr)
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{
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__be64 ret;
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lio_pci_rw_core_mem(oct, coreaddr, (uint8_t *)&ret, 8, 1);
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return (be64toh(ret));
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}
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uint32_t
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lio_read_device_mem32(struct octeon_device *oct, uint64_t coreaddr)
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{
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__be32 ret;
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lio_pci_rw_core_mem(oct, coreaddr, (uint8_t *)&ret, 4, 1);
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return (be32toh(ret));
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}
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void
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lio_write_device_mem32(struct octeon_device *oct, uint64_t coreaddr,
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uint32_t val)
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{
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__be32 t = htobe32(val);
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lio_pci_rw_core_mem(oct, coreaddr, (uint8_t *)&t, 4, 0);
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}
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