9aba06377d
With more ports, some of the registers are shifted a bit to accommodate. This switch also adds two high speed Serdes/SGMII interfaces (2.5 Gb/s). Sponsored by: Rubicon Communications, LLC (Netgate)
306 lines
8.9 KiB
C
306 lines
8.9 KiB
C
/*-
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* Copyright (c) 2015 Semihalf
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* Copyright (c) 2015 Stormshield
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _E6000SWREG_H_
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#define _E6000SWREG_H_
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struct atu_opt {
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uint16_t mac_01;
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uint16_t mac_23;
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uint16_t mac_45;
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uint16_t fid;
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};
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/*
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* Definitions for the Marvell 88E6000 series Ethernet Switch.
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*/
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/* Switch IDs. */
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#define MV88E6141 0x3400
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#define MV88E6341 0x3410
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#define MV88E6352 0x3520
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#define MV88E6172 0x1720
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#define MV88E6176 0x1760
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#define MV88E6190 0x1900
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#define MVSWITCH(_sc, id) ((_sc)->swid == (id))
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#define MVSWITCH_MULTICHIP(_sc) ((_sc)->sw_addr != 0)
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/*
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* Switch Registers
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*/
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#define REG_GLOBAL 0x1b
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#define REG_GLOBAL2 0x1c
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#define REG_PORT(_sc, p) ((MVSWITCH((_sc), MV88E6190) ? 0 : 0x10) + (p))
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#define REG_NUM_MAX 31
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/*
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* Per-Port Switch Registers
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*/
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#define PORT_STATUS 0x0
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#define PORT_STATUS_SPEED_MASK 0x300
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#define PORT_STATUS_SPEED_10 0
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#define PORT_STATUS_SPEED_100 1
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#define PORT_STATUS_SPEED_1000 2
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#define PORT_STATUS_DUPLEX_MASK (1 << 10)
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#define PORT_STATUS_LINK_MASK (1 << 11)
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#define PORT_STATUS_PHY_DETECT_MASK (1 << 12)
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#define PSC_CONTROL 0x1
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#define PSC_CONTROL_FORCED_SPD (1 << 13)
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#define PSC_CONTROL_ALT_SPD (1 << 12)
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#define PSC_CONTROL_EEE_ON (1 << 9)
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#define PSC_CONTROL_FORCED_EEE (1 << 8)
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#define PSC_CONTROL_FC_ON (1 << 7)
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#define PSC_CONTROL_FORCED_FC (1 << 6)
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#define PSC_CONTROL_LINK_UP (1 << 5)
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#define PSC_CONTROL_FORCED_LINK (1 << 4)
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#define PSC_CONTROL_FULLDPX (1 << 3)
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#define PSC_CONTROL_FORCED_DPX (1 << 2)
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#define PSC_CONTROL_SPD10G 0x3
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#define PSC_CONTROL_SPD2500 PSC_CONTROL_SPD10G
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#define PSC_CONTROL_SPD1000 0x2
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#define SWITCH_ID 0x3
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#define PORT_CONTROL 0x4
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#define PORT_CONTROL1 0x5
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#define PORT_CONTROL1_LAG_PORT (1 << 14)
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#define PORT_CONTROL1_LAG_ID_MASK 0xf
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#define PORT_CONTROL1_LAG_ID_SHIFT 8
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#define PORT_CONTROL1_FID_MASK 0xf
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#define PORT_VLAN_MAP 0x6
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#define PORT_VID 0x7
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#define PORT_CONTROL2 0x8
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#define PORT_ASSOCIATION_VECTOR 0xb
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#define PORT_ATU_CTRL 0xc
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#define RX_COUNTER 0x12
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#define TX_COUNTER 0x13
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#define PORT_MASK(_sc) 0x7f
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#define PORT_VID_DEF_VID 0
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#define PORT_VID_DEF_VID_MASK 0xfff
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#define PORT_VID_PRIORITY_MASK 0xc00
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#define PORT_CONTROL_DISABLED 0
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#define PORT_CONTROL_BLOCKING 1
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#define PORT_CONTROL_LEARNING 2
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#define PORT_CONTROL_FORWARDING 3
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#define PORT_CONTROL_ENABLE 3
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#define PORT_CONTROL_FRAME 0x0300
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#define PORT_CONTROL_EGRESS 0x3000
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#define PORT_CONTROL2_DOT1Q 0x0c00
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#define PORT_CONTROL2_DISC_TAGGED (1 << 9)
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#define PORT_CONTROL2_DISC_UNTAGGED (1 << 8)
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/* PORT_VLAN fields */
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#define PORT_VLAN_MAP_FID 12
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#define PORT_VLAN_MAP_FID_MASK 0xf000
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/*
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* Switch Global Register 1 accessed via REG_GLOBAL_ADDR
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*/
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#define SWITCH_GLOBAL_STATUS 0
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#define SWITCH_GLOBAL_STATUS_IR (1 << 11)
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#define SWITCH_GLOBAL_CONTROL 4
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#define SWITCH_GLOBAL_CONTROL2 28
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#define MONITOR_CONTROL 26
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/* VTU operation */
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#define VTU_FID 2
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#define VTU_OPERATION 5
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#define VTU_VID 6
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#define VTU_DATA 7
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#define VTU_DATA2 8
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#define VTU_FID_MASK(_sc) (MVSWITCH((_sc), MV88E6190) ? 0xfff : 0xff)
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#define VTU_FID_POLICY (1 << 12)
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#define VTU_PORT_UNMODIFIED 0
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#define VTU_PORT_UNTAGGED 1
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#define VTU_PORT_TAGGED 2
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#define VTU_PORT_DISCARD 3
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#define VTU_PPREG(_sc) (MVSWITCH((_sc), MV88E6190) ? 8 : 4)
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#define VTU_PORT(_sc, p) (((p) % VTU_PPREG(_sc)) * (16 / VTU_PPREG(_sc)))
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#define VTU_PORT_MASK 3
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#define VTU_BUSY (1 << 15)
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#define VTU_VID_VALID (1 << 12)
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#define VTU_VID_MASK 0xfff
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/* VTU opcodes */
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#define VTU_OP_MASK (7 << 12)
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#define VTU_NOP (0 << 12)
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#define VTU_FLUSH (1 << 12)
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#define VTU_LOAD (3 << 12)
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#define VTU_PURGE (3 << 12)
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#define VTU_GET_NEXT (4 << 12)
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#define STU_LOAD (5 << 12)
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#define STU_PURGE (5 << 12)
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#define STU_GET_NEXT (6 << 12)
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#define VTU_GET_VIOLATION_DATA (7 << 12)
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#define VTU_CLEAR_VIOLATION_DATA (7 << 12)
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/* ATU operation */
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#define ATU_FID 1
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#define ATU_CONTROL 10
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#define ATU_OPERATION 11
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#define ATU_DATA 12
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#define ATU_MAC_ADDR01 13
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#define ATU_MAC_ADDR23 14
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#define ATU_MAC_ADDR45 15
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#define ATU_DATA_LAG (1 << 15)
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#define ATU_PORT_MASK(_sc) (MVSWITCH((_sc), MV88E6190) ? 0xfff0 : 0xff0)
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#define ATU_PORT_SHIFT 4
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#define ATU_LAG_MASK 0xf0
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#define ATU_LAG_SHIFT 4
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#define ATU_STATE_MASK 0xf
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#define ATU_UNIT_BUSY (1 << 15)
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#define ENTRY_STATE 0xf
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/* ATU_CONTROL fields */
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#define ATU_CONTROL_AGETIME 4
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#define ATU_CONTROL_AGETIME_MASK 0xff0
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#define ATU_CONTROL_LEARN2ALL 3
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/* ATU opcode */
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#define ATU_OP_MASK (7 << 12)
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#define NO_OPERATION (0 << 12)
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#define FLUSH_ALL (1 << 12)
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#define FLUSH_NON_STATIC (2 << 12)
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#define LOAD_FROM_FIB (3 << 12)
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#define PURGE_FROM_FIB (3 << 12)
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#define GET_NEXT_IN_FIB (4 << 12)
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#define FLUSH_ALL_IN_FIB (5 << 12)
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#define FLUSH_NON_STATIC_IN_FIB (6 << 12)
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#define GET_VIOLATION_DATA (7 << 12)
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#define CLEAR_VIOLATION_DATA (7 << 12)
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/* ATU Stats */
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#define COUNT_ALL (0 << 0)
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/*
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* Switch Global Register 2 accessed via REG_GLOBAL2_ADDR
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*/
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#define MGMT_EN_2x 2
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#define MGMT_EN_0x 3
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#define SWITCH_MGMT 5
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#define LAG_MASK 7
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#define LAG_MAPPING 8
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#define ATU_STATS 14
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#define MGMT_EN_ALL 0xffff
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#define LAG_UPDATE (1 << 15)
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#define LAG_MASKNUM_SHIFT 12
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#define LAGID_SHIFT 11
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/* SWITCH_MGMT fields */
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#define SWITCH_MGMT_PRI 0
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#define SWITCH_MGMT_PRI_MASK 7
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#define SWITCH_MGMT_RSVD2CPU 3
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#define SWITCH_MGMT_FC_PRI 4
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#define SWITCH_MGMT_FC_PRI_MASK (7 << 4)
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#define SWITCH_MGMT_FORCEFLOW 7
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/* ATU_STATS fields */
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#define ATU_STATS_BIN 14
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#define ATU_STATS_FLAG 12
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/* Offset of SMI registers in multi-chip setup. */
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#define SMI_CMD 0
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#define SMI_DATA 1
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/*
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* 'Switch Global Registers 2' (REG_GLOBAL2).
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*/
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/* EEPROM registers */
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#define EEPROM_CMD 0x14
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#define EEPROM_BUSY (1 << 15)
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#define EEPROM_READ_CMD (4 << 12)
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#define EEPROM_WRITE_CMD (3 << 12)
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#define EEPROM_WRITE_EN (1 << 10)
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#define EEPROM_DATA_MASK 0xff
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#define EEPROM_ADDR 0x15
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/* PHY registers */
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#define SMI_PHY_CMD_REG 0x18
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#define SMI_CMD_BUSY (1 << 15)
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#define SMI_CMD_MODE_C22 (1 << 12)
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#define SMI_CMD_C22_WRITE (1 << 10)
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#define SMI_CMD_C22_READ (2 << 10)
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#define SMI_CMD_OP_C22_WRITE \
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(SMI_CMD_C22_WRITE | SMI_CMD_BUSY | SMI_CMD_MODE_C22)
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#define SMI_CMD_OP_C22_READ \
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(SMI_CMD_C22_READ | SMI_CMD_BUSY | SMI_CMD_MODE_C22)
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#define SMI_CMD_C45 (0 << 12)
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#define SMI_CMD_C45_ADDR (0 << 10)
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#define SMI_CMD_C45_WRITE (1 << 10)
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#define SMI_CMD_C45_READ (3 << 10)
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#define SMI_CMD_OP_C45_ADDR \
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(SMI_CMD_C45_ADDR | SMI_CMD_BUSY | SMI_CMD_C45)
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#define SMI_CMD_OP_C45_WRITE \
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(SMI_CMD_C45_WRITE | SMI_CMD_BUSY | SMI_CMD_C45)
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#define SMI_CMD_OP_C45_READ \
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(SMI_CMD_C45_READ | SMI_CMD_BUSY | SMI_CMD_C45)
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#define SMI_CMD_DEV_ADDR 5
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#define SMI_CMD_DEV_ADDR_MASK 0x3e0
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#define SMI_CMD_REG_ADDR_MASK 0x1f
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#define SMI_PHY_DATA_REG 0x19
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#define PHY_DATA_MASK 0xffff
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#define PHY_PAGE_REG 22
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/*
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* Scratch and Misc register accessed via
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* 'Switch Global Registers' (REG_GLOBAL2)
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*/
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#define SCR_AND_MISC_REG 0x1a
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#define SCR_AND_MISC_PTR_CFG 0x7000
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#define SCR_AND_MISC_DATA_CFG_MASK 0xf0
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/* SERDES registers. */
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#define E6000SW_SERDES_DEV 4
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#define E6000SW_SERDES_PCS_CTL1 0x1000
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#define E6000SW_SERDES_SGMII_CTL 0x2000
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#define E6000SW_SERDES_PDOWN (1 << 11)
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#define E6000SW_NUM_VLANS 128
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#define E6000SW_NUM_LAGMASK 8
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#define E6000SW_NUM_PHY_REGS 29
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#define E6000SW_MAX_PORTS 11
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#define E6000SW_DEFAULT_AGETIME 20
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#define E6000SW_RETRIES 100
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#define E6000SW_SMI_TIMEOUT 16
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#endif /* _E6000SWREG_H_ */
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