6f378116e9
Early versions of the VT-d spec mentioned 6-level paging support as a possible value for the SAGAW capability, but later versions removed it and SAGAW=0x10 is currently listed as a reserved value. The 6-level (agaw=64) entry in sagaw_bits is furthermore problematic with clang15 because the attempted comparison against 1ULL << 64 in dmar_maxaddr2mgaw() causes the compiler to elide the last iteration of the initial loop, which bypasses the subsequent logic to find the greatest HW-supported address width. This results in 5-level paging always being selected regardless of whether the hardware supports it, which can result address translation failure due to invalid context- entry programming. Reviewed by: kib MFC after: 3 days Differential Revision: https://reviews.freebsd.org/D39896 |
||
|---|---|---|
| .. | ||
| intel_ctx.c | ||
| intel_dmar.h | ||
| intel_drv.c | ||
| intel_fault.c | ||
| intel_idpgtbl.c | ||
| intel_intrmap.c | ||
| intel_qi.c | ||
| intel_quirks.c | ||
| intel_reg.h | ||
| intel_utils.c | ||
| iommu_intrmap.h | ||