John Baldwin 2d10570afe Some K8 chipsets don't expose all of the PCI devices on bus 0 via PCIe ... memory-mapped config access. Add a workaround for these systems by checking the first function of each slot on bus 0 using both the memory-mapped config access and the older type 1 I/O port config access. If we find a slot that is only visible via the type 1 I/O port config access, we flag that slot. Future PCI config transactions to flagged slots on bus 0 use type 1 I/O port config access rather than memory mapped config access.		2008-09-10 18:06:08 +00:00
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pci_bus.c	Make the PCI code aware of PCI domains (aka PCI segments) so we can	2007-09-30 11:05:18 +00:00
pci_cfgreg.c	Some K8 chipsets don't expose all of the PCI devices on bus 0 via PCIe	2008-09-10 18:06:08 +00:00