aaaca7e743
The reference driver has a 3ms delay for the AR9130 but I'm not as yet sure why. From what I can gather, it's likely waiting for some FIFO flush to occur. At some point in the future it may be worthwhile adding a WMAC FIFO flush here, but that'd require some side-call through to the SoC DDR flush routines. Obtained from: Atheros
247 lines
6.9 KiB
C
247 lines
6.9 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_desc.h"
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#include "ah_internal.h"
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#include "ar5416/ar5416.h"
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#include "ar5416/ar5416reg.h"
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#include "ar5416/ar5416desc.h"
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/*
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* Get the receive filter.
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*/
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uint32_t
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ar5416GetRxFilter(struct ath_hal *ah)
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{
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uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER);
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uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR);
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if (phybits & AR_PHY_ERR_RADAR)
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bits |= HAL_RX_FILTER_PHYRADAR;
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if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
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bits |= HAL_RX_FILTER_PHYERR;
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return bits;
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}
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/*
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* Set the receive filter.
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*/
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void
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ar5416SetRxFilter(struct ath_hal *ah, u_int32_t bits)
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{
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uint32_t phybits;
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OS_REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff));
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phybits = 0;
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if (bits & HAL_RX_FILTER_PHYRADAR)
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phybits |= AR_PHY_ERR_RADAR;
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if (bits & HAL_RX_FILTER_PHYERR)
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phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
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OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
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if (phybits) {
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OS_REG_WRITE(ah, AR_RXCFG,
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OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
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} else {
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OS_REG_WRITE(ah, AR_RXCFG,
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OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
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}
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}
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/*
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* Stop Receive at the DMA engine
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*/
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HAL_BOOL
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ar5416StopDmaReceive(struct ath_hal *ah)
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{
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HAL_BOOL status;
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OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP);
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OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
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if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
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OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP_ERR);
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#ifdef AH_DEBUG
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ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n"
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"AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
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__func__,
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OS_REG_READ(ah, AR_CR),
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OS_REG_READ(ah, AR_DIAG_SW));
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#endif
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status = AH_FALSE;
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} else {
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status = AH_TRUE;
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}
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/*
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* XXX Is this to flush whatever is in a FIFO somewhere?
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* XXX If so, what should the correct behaviour should be?
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*/
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if (AR_SREV_9100(ah))
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OS_DELAY(3000);
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return (status);
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}
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/*
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* Start receive at the PCU engine
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*/
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void
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ar5416StartPcuReceive(struct ath_hal *ah)
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{
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struct ath_hal_private *ahp = AH_PRIVATE(ah);
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HALDEBUG(ah, HAL_DEBUG_RX, "%s: Start PCU Receive \n", __func__);
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ar5212EnableMibCounters(ah);
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/* NB: restore current settings */
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ar5416AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE);
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/*
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* NB: must do after enabling phy errors to avoid rx
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* frames w/ corrupted descriptor status.
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*/
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OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
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}
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/*
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* Stop receive at the PCU engine
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* and abort current frame in PCU
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*/
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void
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ar5416StopPcuReceive(struct ath_hal *ah)
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{
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OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
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HALDEBUG(ah, HAL_DEBUG_RX, "%s: Stop PCU Receive \n", __func__);
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ar5212DisableMibCounters(ah);
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}
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/*
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* Initialize RX descriptor, by clearing the status and setting
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* the size (and any other flags).
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*/
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HAL_BOOL
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ar5416SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
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uint32_t size, u_int flags)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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HALASSERT((size &~ AR_BufLen) == 0);
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ads->ds_ctl1 = size & AR_BufLen;
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if (flags & HAL_RXDESC_INTREQ)
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ads->ds_ctl1 |= AR_RxIntrReq;
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/* this should be enough */
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ads->ds_rxstatus8 &= ~AR_RxDone;
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/* clear the rest of the status fields */
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OS_MEMZERO(&(ads->u), sizeof(ads->u));
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return AH_TRUE;
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}
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/*
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* Process an RX descriptor, and return the status to the caller.
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* Copy some hardware specific items into the software portion
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* of the descriptor.
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*
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* NB: the caller is responsible for validating the memory contents
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* of the descriptor (e.g. flushing any cached copy).
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*/
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HAL_STATUS
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ar5416ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
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uint32_t pa, struct ath_desc *nds, uint64_t tsf,
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struct ath_rx_status *rs)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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if ((ads->ds_rxstatus8 & AR_RxDone) == 0)
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return HAL_EINPROGRESS;
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rs->rs_status = 0;
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rs->rs_flags = 0;
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rs->rs_datalen = ads->ds_rxstatus1 & AR_DataLen;
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rs->rs_tstamp = ads->AR_RcvTimestamp;
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/* XXX what about KeyCacheMiss? */
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rs->rs_rssi = MS(ads->ds_rxstatus4, AR_RxRSSICombined);
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rs->rs_rssi_ctl[0] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt00);
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rs->rs_rssi_ctl[1] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt01);
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rs->rs_rssi_ctl[2] = MS(ads->ds_rxstatus0, AR_RxRSSIAnt02);
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rs->rs_rssi_ext[0] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt10);
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rs->rs_rssi_ext[1] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt11);
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rs->rs_rssi_ext[2] = MS(ads->ds_rxstatus4, AR_RxRSSIAnt12);
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if (ads->ds_rxstatus8 & AR_RxKeyIdxValid)
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rs->rs_keyix = MS(ads->ds_rxstatus8, AR_KeyIdx);
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else
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rs->rs_keyix = HAL_RXKEYIX_INVALID;
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/* NB: caller expected to do rate table mapping */
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rs->rs_rate = RXSTATUS_RATE(ah, ads);
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rs->rs_more = (ads->ds_rxstatus1 & AR_RxMore) ? 1 : 0;
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rs->rs_isaggr = (ads->ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
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rs->rs_moreaggr = (ads->ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
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rs->rs_antenna = MS(ads->ds_rxstatus3, AR_RxAntenna);
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if (ads->ds_rxstatus3 & AR_GI)
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rs->rs_flags |= HAL_RX_GI;
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if (ads->ds_rxstatus3 & AR_2040)
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rs->rs_flags |= HAL_RX_2040;
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if (ads->ds_rxstatus8 & AR_PreDelimCRCErr)
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rs->rs_flags |= HAL_RX_DELIM_CRC_PRE;
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if (ads->ds_rxstatus8 & AR_PostDelimCRCErr)
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rs->rs_flags |= HAL_RX_DELIM_CRC_POST;
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if (ads->ds_rxstatus8 & AR_DecryptBusyErr)
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rs->rs_flags |= HAL_RX_DECRYPT_BUSY;
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if (ads->ds_rxstatus8 & AR_HiRxChain)
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rs->rs_flags |= HAL_RX_HI_RX_CHAIN;
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if ((ads->ds_rxstatus8 & AR_RxFrameOK) == 0) {
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/*
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* These four bits should not be set together. The
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* 5416 spec states a Michael error can only occur if
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* DecryptCRCErr not set (and TKIP is used). Experience
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* indicates however that you can also get Michael errors
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* when a CRC error is detected, but these are specious.
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* Consequently we filter them out here so we don't
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* confuse and/or complicate drivers.
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*/
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if (ads->ds_rxstatus8 & AR_CRCErr)
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rs->rs_status |= HAL_RXERR_CRC;
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else if (ads->ds_rxstatus8 & AR_PHYErr) {
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u_int phyerr;
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rs->rs_status |= HAL_RXERR_PHY;
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phyerr = MS(ads->ds_rxstatus8, AR_PHYErrCode);
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rs->rs_phyerr = phyerr;
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} else if (ads->ds_rxstatus8 & AR_DecryptCRCErr)
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rs->rs_status |= HAL_RXERR_DECRYPT;
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else if (ads->ds_rxstatus8 & AR_MichaelErr)
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rs->rs_status |= HAL_RXERR_MIC;
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}
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return HAL_OK;
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}
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