Konstantin Belousov 3621ba1ede Add Intel Spec Store Bypass Disable control. ... Speculative Store Bypass (SSB) is a speculative execution side channel vulnerability identified by Jann Horn of Google Project Zero (GPZ) and Ken Johnson of the Microsoft Security Response Center (MSRC) https://bugs.chromium.org/p/project-zero/issues/detail?id=1528. Updated Intel microcode introduces a MSR bit to disable SSB as a mitigation for the vulnerability. Introduce a sysctl hw.spec_store_bypass_disable to provide global control over the SSBD bit, akin to the existing sysctl that controls IBRS. The sysctl can be set to one of three values: 0: off 1: on 2: auto Future work will enable applications to control SSBD on a per-process basis (when it is not enabled globally). SSBD bit detection and control was verified with prerelease microcode. Security: CVE-2018-3639 Tested by: emaste (previous version, without updated microcode) Sponsored by: The FreeBSD Foundation MFC after: 3 days		2018-05-21 21:08:19 +00:00
..
acpica	Add Intel Spec Store Bypass Disable control.	2018-05-21 21:08:19 +00:00
bios	sys/x86: further adoption of SPDX licensing ID tags.	2017-11-27 15:11:47 +00:00
cpufreq	cpufreq: Remove error-prone table terminators in favor of automatic sizing	2018-04-14 03:15:05 +00:00
include	Add Intel Spec Store Bypass Disable control.	2018-05-21 21:08:19 +00:00
iommu	Don't include DMAR map entry zone items in kernel dumps.	2018-02-18 16:03:50 +00:00
isa	ANSIfy sys/x86	2018-03-17 01:40:09 +00:00
pci	Add ISA PNP tables to ISA drivers. Fix a few incidental comments.	2018-01-29 00:22:30 +00:00
x86	Add Intel Spec Store Bypass Disable control.	2018-05-21 21:08:19 +00:00
xen	Fix PCID+PTI pmap operations on Xen/HVM.	2018-05-19 20:28:59 +00:00