dc4ee6ca91
make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
500 lines
20 KiB
C
500 lines
20 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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#define CVMX_USE_1_TO_1_TLB_MAPPINGS 0
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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#include <linux/kernel.h>
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#include <asm/octeon/cvmx.h>
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#include <asm/octeon/cvmx-spinlock.h>
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#include <asm/octeon/octeon-pci-console.h>
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#define MIN(a,b) min((a),(b))
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#else
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#include "cvmx-platform.h"
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#include "cvmx.h"
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#include "cvmx-spinlock.h"
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#ifndef MIN
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# define MIN(a,b) (((a)<(b))?(a):(b))
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#endif
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#include "cvmx-bootmem.h"
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#include "octeon-pci-console.h"
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#endif
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#ifdef __U_BOOT__
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#include <watchdog.h>
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#endif
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#if defined(__linux__) && !defined(__KERNEL__) && !defined(OCTEON_TARGET)
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#include "octeon-pci.h"
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#endif
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/* The following code is only used in standalone CVMX applications. It does
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not apply for kernel or Linux programming */
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#if defined(OCTEON_TARGET) && !defined(__linux__)
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static int cvmx_pci_console_num = 0;
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static int per_core_pci_consoles = 0;
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static uint64_t pci_console_desc_addr = 0;
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/* This function for simple executive internal use only - do not use in any application */
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int __cvmx_pci_console_write (int fd, char *buf, int nbytes)
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{
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int console_num;
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if (fd >= 0x10000000)
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{
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console_num = fd & 0xFFFF;
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}
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else if (per_core_pci_consoles)
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{
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console_num = cvmx_get_core_num();
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}
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else
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console_num = cvmx_pci_console_num;
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if (!pci_console_desc_addr)
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{
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const cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(OCTEON_PCI_CONSOLE_BLOCK_NAME);
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pci_console_desc_addr = block_desc->base_addr;
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}
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return octeon_pci_console_write(pci_console_desc_addr, console_num, buf, nbytes, 0);
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}
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#endif
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#if !defined(CONFIG_OCTEON_U_BOOT) || (defined(CONFIG_OCTEON_U_BOOT) && (defined(CFG_PCI_CONSOLE) || defined(CONFIG_SYS_PCI_CONSOLE)))
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int octeon_pci_console_buffer_free_bytes(uint32_t buffer_size, uint32_t wr_idx, uint32_t rd_idx)
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{
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if (rd_idx >= buffer_size || wr_idx >= buffer_size)
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return -1;
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return (((buffer_size -1) - (wr_idx - rd_idx))%buffer_size);
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}
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int octeon_pci_console_buffer_avail_bytes(uint32_t buffer_size, uint32_t wr_idx, uint32_t rd_idx)
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{
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if (rd_idx >= buffer_size || wr_idx >= buffer_size)
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return -1;
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return (buffer_size - 1 - octeon_pci_console_buffer_free_bytes(buffer_size, wr_idx, rd_idx));
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}
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#endif
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/* The following code is only used under Linux userspace when you are using
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CVMX */
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#if defined(__linux__) && !defined(__KERNEL__) && !defined(OCTEON_TARGET)
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int octeon_pci_console_host_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int write_reqest_size, uint32_t flags)
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{
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if (!console_desc_addr)
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return -1;
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/* Get global pci console information and look up specific console structure. */
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uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
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// printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
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if (console_num >= num_consoles)
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{
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printf("ERROR: attempting to read non-existant console: %d\n", console_num);
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return(-1);
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}
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uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
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// printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
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uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
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/* Check to see if any data is available */
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uint32_t rd_idx, wr_idx;
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uint64_t base_addr;
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base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, input_base_addr));
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rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_read_index));
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wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index));
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// printf("Input base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
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int bytes_to_write = octeon_pci_console_buffer_free_bytes(console_buffer_size, wr_idx, rd_idx);
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if (bytes_to_write <= 0)
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return bytes_to_write;
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bytes_to_write = MIN(bytes_to_write, write_reqest_size);
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/* Check to see if what we want to write is not contiguous, and limit ourselves to the contiguous block*/
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if (wr_idx + bytes_to_write >= console_buffer_size)
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bytes_to_write = console_buffer_size - wr_idx;
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// printf("Attempting to write %d bytes, (buf size: %d)\n", bytes_to_write, write_reqest_size);
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octeon_pci_write_mem(base_addr + wr_idx, buffer, bytes_to_write, OCTEON_PCI_ENDIAN_64BIT_SWAP);
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octeon_write_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index), (wr_idx + bytes_to_write)%console_buffer_size);
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return bytes_to_write;
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}
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int octeon_pci_console_host_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buf_size, uint32_t flags)
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{
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if (!console_desc_addr)
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return -1;
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/* Get global pci console information and look up specific console structure. */
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uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
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// printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
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if (console_num >= num_consoles)
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{
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printf("ERROR: attempting to read non-existant console: %d\n", console_num);
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return(-1);
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}
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uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
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uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
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// printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
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/* Check to see if any data is available */
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uint32_t rd_idx, wr_idx;
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uint64_t base_addr;
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base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, output_base_addr));
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rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index));
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wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_write_index));
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// printf("Read buffer base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
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int bytes_to_read = octeon_pci_console_buffer_avail_bytes(console_buffer_size, wr_idx, rd_idx);
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if (bytes_to_read <= 0)
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return bytes_to_read;
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bytes_to_read = MIN(bytes_to_read, buf_size);
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/* Check to see if what we want to read is not contiguous, and limit ourselves to the contiguous block*/
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if (rd_idx + bytes_to_read >= console_buffer_size)
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bytes_to_read = console_buffer_size - rd_idx;
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octeon_pci_read_mem(buffer, base_addr + rd_idx, bytes_to_read,OCTEON_PCI_ENDIAN_64BIT_SWAP);
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octeon_write_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index), (rd_idx + bytes_to_read)%console_buffer_size);
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return bytes_to_read;
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}
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int octeon_pci_console_host_write_avail(uint64_t console_desc_addr, unsigned int console_num)
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{
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if (!console_desc_addr)
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return -1;
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/* Get global pci console information and look up specific console structure. */
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uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
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// printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
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if (console_num >= num_consoles)
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{
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printf("ERROR: attempting to read non-existant console: %d\n", console_num);
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return -1;
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}
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uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
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// printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
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uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
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/* Check to see if any data is available */
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uint32_t rd_idx, wr_idx;
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uint64_t base_addr;
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base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, input_base_addr));
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rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_read_index));
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wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index));
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// printf("Input base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
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return octeon_pci_console_buffer_free_bytes(console_buffer_size, wr_idx, rd_idx);
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}
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int octeon_pci_console_host_read_avail(uint64_t console_desc_addr, unsigned int console_num)
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{
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if (!console_desc_addr)
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return -1;
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/* Get global pci console information and look up specific console structure. */
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uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
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// printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
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if (console_num >= num_consoles)
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{
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printf("ERROR: attempting to read non-existant console: %d\n", console_num);
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return(-1);
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}
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uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
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uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
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// printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
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/* Check to see if any data is available */
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uint32_t rd_idx, wr_idx;
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uint64_t base_addr;
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base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, output_base_addr));
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rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index));
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wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_write_index));
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// printf("Read buffer base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
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return octeon_pci_console_buffer_avail_bytes(console_buffer_size, wr_idx, rd_idx);
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}
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#endif /* TARGET_HOST */
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/* This code is only available in a kernel or CVMX standalone. It can't be used
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from userspace */
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#if (!defined(CONFIG_OCTEON_U_BOOT) && (!defined(__linux__) || defined(__KERNEL__))) || (defined(CONFIG_OCTEON_U_BOOT) && (defined(CFG_PCI_CONSOLE) || defined(CONFIG_SYS_PCI_CONSOLE)))
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static octeon_pci_console_t *octeon_pci_console_get_ptr(uint64_t console_desc_addr, unsigned int console_num)
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{
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octeon_pci_console_desc_t *cons_desc_ptr;
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if (!console_desc_addr)
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return NULL;
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cons_desc_ptr = (octeon_pci_console_desc_t *)cvmx_phys_to_ptr(console_desc_addr);
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if (console_num >= cons_desc_ptr->num_consoles)
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return NULL;
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return (octeon_pci_console_t *)cvmx_phys_to_ptr(cons_desc_ptr->console_addr_array[console_num]);
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}
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int octeon_pci_console_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int bytes_to_write, uint32_t flags)
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{
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octeon_pci_console_t *cons_ptr;
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cvmx_spinlock_t *lock;
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int bytes_available;
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char *buf_ptr;
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int bytes_written;
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cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
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if (!cons_ptr)
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return -1;
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lock = (cvmx_spinlock_t *)&cons_ptr->lock;
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buf_ptr = (char*)cvmx_phys_to_ptr(cons_ptr->output_base_addr);
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bytes_written = 0;
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cvmx_spinlock_lock(lock);
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while (bytes_to_write > 0)
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{
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bytes_available = octeon_pci_console_buffer_free_bytes(cons_ptr->buf_size, cons_ptr->output_write_index, cons_ptr->output_read_index);
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// printf("Console %d has %d bytes available for writes\n", console_num, bytes_available);
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if (bytes_available > 0)
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{
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int write_size = MIN(bytes_available, bytes_to_write);
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/* Limit ourselves to what we can output in a contiguous block */
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if (cons_ptr->output_write_index + write_size >= cons_ptr->buf_size)
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write_size = cons_ptr->buf_size - cons_ptr->output_write_index;
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memcpy(buf_ptr + cons_ptr->output_write_index, buffer + bytes_written, write_size);
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CVMX_SYNCW; /* Make sure data is visible before changing write index */
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cons_ptr->output_write_index = (cons_ptr->output_write_index + write_size)%cons_ptr->buf_size;
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bytes_to_write -= write_size;
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bytes_written += write_size;
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}
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else if (bytes_available == 0)
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{
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/* Check to see if we should wait for room, or return after a partial write */
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if (flags & OCT_PCI_CON_FLAG_NONBLOCK)
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goto done;
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#ifdef __U_BOOT__
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WATCHDOG_RESET();
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#endif
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cvmx_wait(1000000); /* Delay if we are spinning */
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}
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else
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{
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bytes_written = -1;
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goto done;
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}
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}
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done:
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cvmx_spinlock_unlock(lock);
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return(bytes_written);
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}
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int octeon_pci_console_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buffer_size, uint32_t flags)
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{
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int bytes_available;
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char *buf_ptr;
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cvmx_spinlock_t *lock;
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int bytes_read;
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int read_size;
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octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
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if (!cons_ptr)
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return -1;
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buf_ptr = (char*)cvmx_phys_to_ptr(cons_ptr->input_base_addr);
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bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index);
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if (bytes_available < 0)
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return bytes_available;
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lock = (cvmx_spinlock_t *)&cons_ptr->lock;
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cvmx_spinlock_lock(lock);
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if (!(flags & OCT_PCI_CON_FLAG_NONBLOCK))
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{
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/* Wait for some data to be available */
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while (0 == (bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index)))
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{
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cvmx_wait(1000000);
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#ifdef __U_BOOT__
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WATCHDOG_RESET();
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#endif
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}
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}
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bytes_read = 0;
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// printf("Console %d has %d bytes available for writes\n", console_num, bytes_available);
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/* Don't overflow the buffer passed to us */
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read_size = MIN(bytes_available, buffer_size);
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/* Limit ourselves to what we can input in a contiguous block */
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if (cons_ptr->input_read_index + read_size >= cons_ptr->buf_size)
|
|
read_size = cons_ptr->buf_size - cons_ptr->input_read_index;
|
|
|
|
memcpy(buffer, buf_ptr + cons_ptr->input_read_index, read_size);
|
|
cons_ptr->input_read_index = (cons_ptr->input_read_index + read_size)%cons_ptr->buf_size;
|
|
bytes_read += read_size;
|
|
|
|
cvmx_spinlock_unlock(lock);
|
|
return(bytes_read);
|
|
}
|
|
|
|
|
|
int octeon_pci_console_write_avail(uint64_t console_desc_addr, unsigned int console_num)
|
|
{
|
|
int bytes_available;
|
|
octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
|
|
if (!cons_ptr)
|
|
return -1;
|
|
|
|
bytes_available = octeon_pci_console_buffer_free_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index);
|
|
if (bytes_available >= 0)
|
|
return(bytes_available);
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
|
|
int octeon_pci_console_read_avail(uint64_t console_desc_addr, unsigned int console_num)
|
|
{
|
|
int bytes_available;
|
|
octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
|
|
if (!cons_ptr)
|
|
return -1;
|
|
|
|
bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index);
|
|
if (bytes_available >= 0)
|
|
return(bytes_available);
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
/* This code can only be used in the bootloader */
|
|
#if defined(CONFIG_OCTEON_U_BOOT) && (defined(CFG_PCI_CONSOLE) || defined(CONFIG_SYS_PCI_CONSOLE))
|
|
uint64_t octeon_pci_console_init(int num_consoles, int buffer_size)
|
|
{
|
|
octeon_pci_console_desc_t *cons_desc_ptr;
|
|
octeon_pci_console_t *cons_ptr;
|
|
|
|
/* Compute size required for pci console structure */
|
|
int alloc_size = num_consoles * (buffer_size * 2 + sizeof(octeon_pci_console_t) + sizeof(uint64_t)) + sizeof(octeon_pci_console_desc_t);
|
|
|
|
/* Allocate memory for the consoles. This must be in the range addresssible by the bootloader.
|
|
** Try to do so in a manner which minimizes fragmentation. We try to put it at the top of DDR0 or bottom of
|
|
** DDR2 first, and only do generic allocation if those fail */
|
|
int64_t console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, OCTEON_DDR0_SIZE - alloc_size - 128, OCTEON_DDR0_SIZE, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
|
|
if (console_block_addr < 0)
|
|
console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, OCTEON_DDR2_BASE + 1, OCTEON_DDR2_BASE + alloc_size + 128, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
|
|
if (console_block_addr < 0)
|
|
console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, 0, 0x7fffffff, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
|
|
if (console_block_addr < 0)
|
|
return 0;
|
|
|
|
cons_desc_ptr = (void *)(uint32_t)console_block_addr;
|
|
|
|
memset(cons_desc_ptr, 0, alloc_size); /* Clear entire alloc'ed memory */
|
|
|
|
cons_desc_ptr->lock = 1; /* initialize as locked until we are done */
|
|
CVMX_SYNCW;
|
|
cons_desc_ptr->num_consoles = num_consoles;
|
|
cons_desc_ptr->flags = 0;
|
|
cons_desc_ptr->major_version = OCTEON_PCI_CONSOLE_MAJOR_VERSION;
|
|
cons_desc_ptr->minor_version = OCTEON_PCI_CONSOLE_MINOR_VERSION;
|
|
|
|
int i;
|
|
uint64_t avail_addr = console_block_addr + sizeof(octeon_pci_console_desc_t) + num_consoles * sizeof(uint64_t);
|
|
for (i = 0; i < num_consoles;i++)
|
|
{
|
|
cons_desc_ptr->console_addr_array[i] = avail_addr;
|
|
cons_ptr = (void *)(uint32_t)cons_desc_ptr->console_addr_array[i];
|
|
avail_addr += sizeof(octeon_pci_console_t);
|
|
cons_ptr->input_base_addr = avail_addr;
|
|
avail_addr += buffer_size;
|
|
cons_ptr->output_base_addr = avail_addr;
|
|
avail_addr += buffer_size;
|
|
cons_ptr->buf_size = buffer_size;
|
|
}
|
|
CVMX_SYNCW;
|
|
cons_desc_ptr->lock = 0;
|
|
|
|
return console_block_addr;
|
|
|
|
|
|
}
|
|
#endif
|