Both RK3328 and RK3399 don't have GPIO_VER_ID register. Set gpio version depending on compat string of the parent.
823 lines
20 KiB
C
823 lines
20 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
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* Copyright (c) 2021 Soren Schmidt <sos@deepcore.dk>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/intr.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk.h>
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#include "gpio_if.h"
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#include "pic_if.h"
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#include "fdt_pinctrl_if.h"
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enum gpio_regs {
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RK_GPIO_SWPORTA_DR = 1, /* Data register */
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RK_GPIO_SWPORTA_DDR, /* Data direction register */
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RK_GPIO_INTEN, /* Interrupt enable register */
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RK_GPIO_INTMASK, /* Interrupt mask register */
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RK_GPIO_INTTYPE_LEVEL, /* Interrupt level register */
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RK_GPIO_INTTYPE_BOTH, /* Both rise and falling edge */
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RK_GPIO_INT_POLARITY, /* Interrupt polarity register */
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RK_GPIO_INT_STATUS, /* Interrupt status register */
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RK_GPIO_INT_RAWSTATUS, /* Raw Interrupt status register */
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RK_GPIO_DEBOUNCE, /* Debounce enable register */
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RK_GPIO_PORTA_EOI, /* Clear interrupt register */
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RK_GPIO_EXT_PORTA, /* External port register */
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RK_GPIO_REGNUM
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};
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#define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */
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#define RK_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
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GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_EDGE_BOTH | \
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GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | \
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GPIO_INTR_LEVEL_HIGH | GPIO_INTR_LEVEL_LOW)
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#define GPIO_FLAGS_PINCTRL GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN
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#define RK_GPIO_MAX_PINS 32
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struct pin_cached {
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uint8_t is_gpio;
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uint32_t flags;
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};
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struct rk_pin_irqsrc {
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struct intr_irqsrc isrc;
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uint32_t irq;
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uint32_t mode;
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};
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struct rk_gpio_softc {
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device_t sc_dev;
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device_t sc_busdev;
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struct mtx sc_mtx;
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struct resource *sc_res[2];
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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clk_t clk;
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device_t pinctrl;
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uint32_t swporta;
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uint32_t swporta_ddr;
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uint32_t version;
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struct pin_cached pin_cached[RK_GPIO_MAX_PINS];
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uint8_t regs[RK_GPIO_REGNUM];
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void *ihandle;
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struct rk_pin_irqsrc isrcs[RK_GPIO_MAX_PINS];
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};
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static struct ofw_compat_data compat_data[] = {
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{"rockchip,gpio-bank", 1},
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{NULL, 0}
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};
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static struct resource_spec rk_gpio_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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#define RK_GPIO_VERSION 0x78
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#define RK_GPIO_TYPE_V1 0x00000000
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#define RK_GPIO_TYPE_V2 0x01000c2b
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#define RK_GPIO_ISRC(sc, irq) (&(sc->isrcs[irq].isrc))
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static int rk_gpio_detach(device_t dev);
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#define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
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#define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
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#define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
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#define RK_GPIO_WRITE(_sc, _off, _val) \
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bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
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#define RK_GPIO_READ(_sc, _off) \
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bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
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static int
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rk_gpio_read_bit(struct rk_gpio_softc *sc, int reg, int bit)
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{
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int offset = sc->regs[reg];
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uint32_t value;
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if (sc->version == RK_GPIO_TYPE_V1) {
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value = RK_GPIO_READ(sc, offset);
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value >>= bit;
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} else {
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value = RK_GPIO_READ(sc, bit > 15 ? offset + 4 : offset);
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value >>= (bit % 16);
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}
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return (value & 1);
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}
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static void
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rk_gpio_write_bit(struct rk_gpio_softc *sc, int reg, int bit, int data)
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{
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int offset = sc->regs[reg];
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uint32_t value;
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if (sc->version == RK_GPIO_TYPE_V1) {
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value = RK_GPIO_READ(sc, offset);
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if (data)
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value |= (1 << bit);
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else
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value &= ~(1 << bit);
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RK_GPIO_WRITE(sc, offset, value);
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} else {
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if (data)
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value = (1 << (bit % 16));
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else
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value = 0;
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value |= (1 << ((bit % 16) + 16));
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RK_GPIO_WRITE(sc, bit > 15 ? offset + 4 : offset, value);
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}
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}
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static uint32_t
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rk_gpio_read_4(struct rk_gpio_softc *sc, int reg)
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{
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int offset = sc->regs[reg];
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uint32_t value;
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if (sc->version == RK_GPIO_TYPE_V1)
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value = RK_GPIO_READ(sc, offset);
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else
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value = (RK_GPIO_READ(sc, offset) & 0xffff) |
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(RK_GPIO_READ(sc, offset + 4) << 16);
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return (value);
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}
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static void
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rk_gpio_write_4(struct rk_gpio_softc *sc, int reg, uint32_t value)
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{
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int offset = sc->regs[reg];
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if (sc->version == RK_GPIO_TYPE_V1)
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RK_GPIO_WRITE(sc, offset, value);
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else {
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RK_GPIO_WRITE(sc, offset, (value & 0xffff) | 0xffff0000);
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RK_GPIO_WRITE(sc, offset + 4, (value >> 16) | 0xffff0000);
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}
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}
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static int
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rk_gpio_intr(void *arg)
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{
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struct rk_gpio_softc *sc = (struct rk_gpio_softc *)arg;;
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struct trapframe *tf = curthread->td_intr_frame;
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uint32_t status;
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RK_GPIO_LOCK(sc);
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status = rk_gpio_read_4(sc, RK_GPIO_INT_STATUS);
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rk_gpio_write_4(sc, RK_GPIO_PORTA_EOI, status);
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RK_GPIO_UNLOCK(sc);
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while (status) {
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int pin = ffs(status) - 1;
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status &= ~(1 << pin);
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if (intr_isrc_dispatch(RK_GPIO_ISRC(sc, pin), tf)) {
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device_printf(sc->sc_dev, "Interrupt pin=%d unhandled\n",
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pin);
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continue;
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}
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if ((sc->version == RK_GPIO_TYPE_V1) &&
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(sc->isrcs[pin].mode & GPIO_INTR_EDGE_BOTH)) {
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RK_GPIO_LOCK(sc);
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if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin))
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rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY,
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(1 << pin), 0);
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else
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rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY,
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(1 << pin), 1);
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RK_GPIO_UNLOCK(sc);
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}
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}
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return (FILTER_HANDLED);
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}
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static int
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rk_gpio_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "RockChip GPIO Bank controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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rk_gpio_attach(device_t dev)
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{
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struct rk_gpio_softc *sc;
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phandle_t parent_node, node;
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int err, i;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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sc->pinctrl = device_get_parent(dev);
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parent_node = ofw_bus_get_node(sc->pinctrl);
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node = ofw_bus_get_node(sc->sc_dev);
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if (!OF_hasprop(node, "gpio-controller"))
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return (ENXIO);
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mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN);
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if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) {
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device_printf(dev, "could not allocate resources\n");
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bus_release_resources(dev, rk_gpio_spec, sc->sc_res);
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mtx_destroy(&sc->sc_mtx);
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return (ENXIO);
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}
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sc->sc_bst = rman_get_bustag(sc->sc_res[0]);
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sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]);
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if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) {
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device_printf(dev, "Cannot get clock\n");
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rk_gpio_detach(dev);
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return (ENXIO);
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}
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err = clk_enable(sc->clk);
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if (err != 0) {
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device_printf(dev, "Could not enable clock %s\n",
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clk_get_name(sc->clk));
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rk_gpio_detach(dev);
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return (ENXIO);
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}
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if ((err = bus_setup_intr(dev, sc->sc_res[1],
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INTR_TYPE_MISC | INTR_MPSAFE, rk_gpio_intr, NULL,
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sc, &sc->ihandle))) {
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device_printf(dev, "Can not setup IRQ\n");
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rk_gpio_detach(dev);
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return (ENXIO);
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}
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/*
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* RK3568 has GPIO_VER_ID register, however both
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* RK3328 and RK3399 doesn't have. So choose the
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* version based on parent's compat string.
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*/
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if (ofw_bus_node_is_compatible(parent_node, "rockchip,rk3568-pinctrl"))
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sc->version = RK_GPIO_TYPE_V2;
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else
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sc->version = RK_GPIO_TYPE_V1;
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switch (sc->version) {
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case RK_GPIO_TYPE_V1:
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sc->regs[RK_GPIO_SWPORTA_DR] = 0x00;
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sc->regs[RK_GPIO_SWPORTA_DDR] = 0x04;
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sc->regs[RK_GPIO_INTEN] = 0x30;
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sc->regs[RK_GPIO_INTMASK] = 0x34;
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sc->regs[RK_GPIO_INTTYPE_LEVEL] = 0x38;
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sc->regs[RK_GPIO_INT_POLARITY] = 0x3c;
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sc->regs[RK_GPIO_INT_STATUS] = 0x40;
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sc->regs[RK_GPIO_INT_RAWSTATUS] = 0x44;
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sc->regs[RK_GPIO_DEBOUNCE] = 0x48;
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sc->regs[RK_GPIO_PORTA_EOI] = 0x4c;
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sc->regs[RK_GPIO_EXT_PORTA] = 0x50;
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break;
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case RK_GPIO_TYPE_V2:
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sc->regs[RK_GPIO_SWPORTA_DR] = 0x00;
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sc->regs[RK_GPIO_SWPORTA_DDR] = 0x08;
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sc->regs[RK_GPIO_INTEN] = 0x10;
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sc->regs[RK_GPIO_INTMASK] = 0x18;
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sc->regs[RK_GPIO_INTTYPE_LEVEL] = 0x20;
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sc->regs[RK_GPIO_INTTYPE_BOTH] = 0x30;
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sc->regs[RK_GPIO_INT_POLARITY] = 0x28;
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sc->regs[RK_GPIO_INT_STATUS] = 0x50;
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sc->regs[RK_GPIO_INT_RAWSTATUS] = 0x58;
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sc->regs[RK_GPIO_DEBOUNCE] = 0x38;
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sc->regs[RK_GPIO_PORTA_EOI] = 0x60;
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sc->regs[RK_GPIO_EXT_PORTA] = 0x70;
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break;
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default:
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device_printf(dev, "Unknown gpio version %08x\n", sc->version);
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rk_gpio_detach(dev);
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return (ENXIO);
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}
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for (i = 0; i < RK_GPIO_MAX_PINS; i++) {
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sc->isrcs[i].irq = i;
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sc->isrcs[i].mode = GPIO_INTR_CONFORM;
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if ((err = intr_isrc_register(RK_GPIO_ISRC(sc, i),
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dev, 0, "%s", device_get_nameunit(dev)))) {
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device_printf(dev, "Can not register isrc %d\n", err);
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rk_gpio_detach(dev);
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return (ENXIO);
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}
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}
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if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) {
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device_printf(dev, "Can not register pic\n");
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rk_gpio_detach(dev);
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return (ENXIO);
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}
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sc->sc_busdev = gpiobus_attach_bus(dev);
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if (sc->sc_busdev == NULL) {
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rk_gpio_detach(dev);
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return (ENXIO);
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}
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/* Set the cached value to unknown */
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for (i = 0; i < RK_GPIO_MAX_PINS; i++)
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sc->pin_cached[i].is_gpio = 2;
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RK_GPIO_LOCK(sc);
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sc->swporta = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR);
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sc->swporta_ddr = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR);
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RK_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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rk_gpio_detach(device_t dev)
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{
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struct rk_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (sc->sc_busdev)
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gpiobus_detach_bus(dev);
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bus_release_resources(dev, rk_gpio_spec, sc->sc_res);
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mtx_destroy(&sc->sc_mtx);
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clk_disable(sc->clk);
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return(0);
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}
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static device_t
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rk_gpio_get_bus(device_t dev)
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{
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struct rk_gpio_softc *sc;
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sc = device_get_softc(dev);
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return (sc->sc_busdev);
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}
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static int
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rk_gpio_pin_max(device_t dev, int *maxpin)
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{
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/* Each bank have always 32 pins */
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/* XXX not true*/
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*maxpin = 31;
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return (0);
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}
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static int
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rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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struct rk_gpio_softc *sc;
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uint32_t bank;
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sc = device_get_softc(dev);
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if (pin >= 32)
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return (EINVAL);
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bank = pin / 8;
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pin = pin - (bank * 8);
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RK_GPIO_LOCK(sc);
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snprintf(name, GPIOMAXNAME, "P%c%d", bank + 'A', pin);
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RK_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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{
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struct rk_gpio_softc *sc;
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int rv;
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sc = device_get_softc(dev);
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if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) {
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rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio);
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if (rv != 0)
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return (rv);
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if (sc->pin_cached[pin].is_gpio == 0)
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return (EINVAL);
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}
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*flags = 0;
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rv = FDT_PINCTRL_GET_FLAGS(sc->pinctrl, dev, pin, flags);
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if (rv != 0)
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return (rv);
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sc->pin_cached[pin].flags = *flags;
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if (sc->swporta_ddr & (1 << pin))
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*flags |= GPIO_PIN_OUTPUT;
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else
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*flags |= GPIO_PIN_INPUT;
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return (0);
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}
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static int
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rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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if (pin >= RK_GPIO_MAX_PINS)
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return EINVAL;
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*caps = RK_GPIO_DEFAULT_CAPS;
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return (0);
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}
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|
|
static int
|
|
rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
|
|
{
|
|
struct rk_gpio_softc *sc;
|
|
int rv;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (pin >= RK_GPIO_MAX_PINS)
|
|
return (EINVAL);
|
|
|
|
if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) {
|
|
rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio);
|
|
if (rv != 0)
|
|
return (rv);
|
|
if (sc->pin_cached[pin].is_gpio == 0)
|
|
return (EINVAL);
|
|
}
|
|
|
|
if (__predict_false((flags & GPIO_PIN_INPUT) && ((flags & GPIO_FLAGS_PINCTRL) != sc->pin_cached[pin].flags))) {
|
|
rv = FDT_PINCTRL_SET_FLAGS(sc->pinctrl, dev, pin, flags);
|
|
sc->pin_cached[pin].flags = flags & GPIO_FLAGS_PINCTRL;
|
|
if (rv != 0)
|
|
return (rv);
|
|
}
|
|
|
|
RK_GPIO_LOCK(sc);
|
|
if (flags & GPIO_PIN_INPUT)
|
|
sc->swporta_ddr &= ~(1 << pin);
|
|
else if (flags & GPIO_PIN_OUTPUT)
|
|
sc->swporta_ddr |= (1 << pin);
|
|
|
|
rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, sc->swporta_ddr);
|
|
RK_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
|
|
{
|
|
struct rk_gpio_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (pin >= RK_GPIO_MAX_PINS)
|
|
return (EINVAL);
|
|
|
|
RK_GPIO_LOCK(sc);
|
|
*val = rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin);
|
|
RK_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
|
|
{
|
|
struct rk_gpio_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (pin >= RK_GPIO_MAX_PINS)
|
|
return (EINVAL);
|
|
|
|
RK_GPIO_LOCK(sc);
|
|
if (value)
|
|
sc->swporta |= (1 << pin);
|
|
else
|
|
sc->swporta &= ~(1 << pin);
|
|
rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta);
|
|
RK_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
rk_gpio_pin_toggle(device_t dev, uint32_t pin)
|
|
{
|
|
struct rk_gpio_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (pin >= RK_GPIO_MAX_PINS)
|
|
return (EINVAL);
|
|
|
|
RK_GPIO_LOCK(sc);
|
|
if (sc->swporta & (1 << pin))
|
|
sc->swporta &= ~(1 << pin);
|
|
else
|
|
sc->swporta |= (1 << pin);
|
|
rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta);
|
|
RK_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
|
|
uint32_t change_pins, uint32_t *orig_pins)
|
|
{
|
|
struct rk_gpio_softc *sc;
|
|
uint32_t reg;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
RK_GPIO_LOCK(sc);
|
|
reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR);
|
|
if (orig_pins)
|
|
*orig_pins = reg;
|
|
sc->swporta = reg;
|
|
|
|
if ((clear_pins | change_pins) != 0) {
|
|
reg = (reg & ~clear_pins) ^ change_pins;
|
|
rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, reg);
|
|
}
|
|
RK_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
|
|
uint32_t *pin_flags)
|
|
{
|
|
struct rk_gpio_softc *sc;
|
|
uint32_t reg, set, mask, flags;
|
|
int i;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (first_pin != 0 || num_pins > 32)
|
|
return (EINVAL);
|
|
|
|
set = 0;
|
|
mask = 0;
|
|
for (i = 0; i < num_pins; i++) {
|
|
mask = (mask << 1) | 1;
|
|
flags = pin_flags[i];
|
|
if (flags & GPIO_PIN_INPUT) {
|
|
set &= ~(1 << i);
|
|
} else if (flags & GPIO_PIN_OUTPUT) {
|
|
set |= (1 << i);
|
|
}
|
|
}
|
|
|
|
RK_GPIO_LOCK(sc);
|
|
reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR);
|
|
reg &= ~mask;
|
|
reg |= set;
|
|
rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, reg);
|
|
sc->swporta_ddr = reg;
|
|
RK_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
|
|
pcell_t *gpios, uint32_t *pin, uint32_t *flags)
|
|
{
|
|
|
|
/* The gpios are mapped as <pin flags> */
|
|
*pin = gpios[0];
|
|
*flags = gpios[1];
|
|
return (0);
|
|
}
|
|
|
|
static phandle_t
|
|
rk_gpio_get_node(device_t bus, device_t dev)
|
|
{
|
|
|
|
/* We only have one child, the GPIO bus, which needs our own node. */
|
|
return (ofw_bus_get_node(bus));
|
|
}
|
|
|
|
static int
|
|
rk_pic_map_intr(device_t dev, struct intr_map_data *data,
|
|
struct intr_irqsrc **isrcp)
|
|
{
|
|
struct rk_gpio_softc *sc = device_get_softc(dev);
|
|
struct intr_map_data_gpio *gdata;
|
|
uint32_t irq;
|
|
|
|
if (data->type != INTR_MAP_DATA_GPIO) {
|
|
device_printf(dev, "Wrong type\n");
|
|
return (ENOTSUP);
|
|
}
|
|
gdata = (struct intr_map_data_gpio *)data;
|
|
irq = gdata->gpio_pin_num;
|
|
if (irq >= RK_GPIO_MAX_PINS) {
|
|
device_printf(dev, "Invalid interrupt %u\n", irq);
|
|
return (EINVAL);
|
|
}
|
|
*isrcp = RK_GPIO_ISRC(sc, irq);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
rk_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
|
|
struct resource *res, struct intr_map_data *data)
|
|
{
|
|
struct rk_gpio_softc *sc = device_get_softc(dev);
|
|
struct rk_pin_irqsrc *rkisrc = (struct rk_pin_irqsrc *)isrc;
|
|
struct intr_map_data_gpio *gdata;
|
|
uint32_t mode;
|
|
uint8_t pin;
|
|
|
|
if (!data) {
|
|
device_printf(dev, "No map data\n");
|
|
return (ENOTSUP);
|
|
}
|
|
gdata = (struct intr_map_data_gpio *)data;
|
|
mode = gdata->gpio_intr_mode;
|
|
pin = gdata->gpio_pin_num;
|
|
|
|
if (rkisrc->irq != gdata->gpio_pin_num) {
|
|
device_printf(dev, "Interrupts don't match\n");
|
|
return (EINVAL);
|
|
}
|
|
|
|
if (isrc->isrc_handlers != 0) {
|
|
device_printf(dev, "Handler already attached\n");
|
|
return (rkisrc->mode == mode ? 0 : EINVAL);
|
|
}
|
|
rkisrc->mode = mode;
|
|
|
|
RK_GPIO_LOCK(sc);
|
|
|
|
switch (mode & GPIO_INTR_MASK) {
|
|
case GPIO_INTR_EDGE_RISING:
|
|
rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0);
|
|
rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1);
|
|
rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1);
|
|
break;
|
|
case GPIO_INTR_EDGE_FALLING:
|
|
rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0);
|
|
rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1);
|
|
rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0);
|
|
break;
|
|
case GPIO_INTR_EDGE_BOTH:
|
|
rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0);
|
|
rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1);
|
|
if (sc->version == RK_GPIO_TYPE_V1) {
|
|
if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin))
|
|
rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY,
|
|
pin, 0);
|
|
else
|
|
rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY,
|
|
pin, 1);
|
|
} else
|
|
rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_BOTH, pin, 1);
|
|
break;
|
|
case GPIO_INTR_LEVEL_HIGH:
|
|
rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0);
|
|
rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0);
|
|
rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1);
|
|
break;
|
|
case GPIO_INTR_LEVEL_LOW:
|
|
rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0);
|
|
rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0);
|
|
rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0);
|
|
break;
|
|
default:
|
|
rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 1);
|
|
rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 0);
|
|
RK_GPIO_UNLOCK(sc);
|
|
return (EINVAL);
|
|
}
|
|
rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, pin, 1);
|
|
rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 0);
|
|
rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 1);
|
|
RK_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
rk_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
|
|
struct resource *res, struct intr_map_data *data)
|
|
{
|
|
struct rk_gpio_softc *sc = device_get_softc(dev);
|
|
struct rk_pin_irqsrc *irqsrc;
|
|
|
|
irqsrc = (struct rk_pin_irqsrc *)isrc;
|
|
|
|
if (isrc->isrc_handlers == 0) {
|
|
irqsrc->mode = GPIO_INTR_CONFORM;
|
|
RK_GPIO_LOCK(sc);
|
|
rk_gpio_write_bit(sc, RK_GPIO_INTEN, irqsrc->irq, 0);
|
|
rk_gpio_write_bit(sc, RK_GPIO_INTMASK, irqsrc->irq, 0);
|
|
rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, irqsrc->irq, 0);
|
|
RK_GPIO_UNLOCK(sc);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t rk_gpio_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, rk_gpio_probe),
|
|
DEVMETHOD(device_attach, rk_gpio_attach),
|
|
DEVMETHOD(device_detach, rk_gpio_detach),
|
|
|
|
/* GPIO protocol */
|
|
DEVMETHOD(gpio_get_bus, rk_gpio_get_bus),
|
|
DEVMETHOD(gpio_pin_max, rk_gpio_pin_max),
|
|
DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname),
|
|
DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags),
|
|
DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps),
|
|
DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags),
|
|
DEVMETHOD(gpio_pin_get, rk_gpio_pin_get),
|
|
DEVMETHOD(gpio_pin_set, rk_gpio_pin_set),
|
|
DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle),
|
|
DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32),
|
|
DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32),
|
|
DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios),
|
|
|
|
/* Interrupt controller interface */
|
|
DEVMETHOD(pic_map_intr, rk_pic_map_intr),
|
|
DEVMETHOD(pic_setup_intr, rk_pic_setup_intr),
|
|
DEVMETHOD(pic_teardown_intr, rk_pic_teardown_intr),
|
|
|
|
/* ofw_bus interface */
|
|
DEVMETHOD(ofw_bus_get_node, rk_gpio_get_node),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t rk_gpio_driver = {
|
|
"gpio",
|
|
rk_gpio_methods,
|
|
sizeof(struct rk_gpio_softc),
|
|
};
|
|
|
|
/*
|
|
* GPIO driver is always a child of rk_pinctrl driver and should be probed
|
|
* and attached within rk_pinctrl_attach function. Due to this, bus pass order
|
|
* must be same as bus pass order of rk_pinctrl driver.
|
|
*/
|
|
EARLY_DRIVER_MODULE(rk_gpio, simplebus, rk_gpio_driver, 0, 0,
|
|
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
|