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1. checking whether there's a link before initializing devices on the bus. When there's no link any access onto the bus will wedge the CPU. 2. synthesizing the class & subclass so that the host controller appears as a standard PCI bridge, rather than a PowerPC CPU. |
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.. | ||
aim | ||
booke | ||
compile | ||
conf | ||
cpufreq | ||
fpu | ||
include | ||
mpc85xx | ||
ofw | ||
powermac | ||
powerpc | ||
psim |