3e13ea16a6
An attempt to write to FCR register may corrupt transmit FIFO, so we should wait for the FIFO to be empty before we can modify it. MFC after: 1 week |
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| .. | ||
| allwinner | ||
| altera/socfpga | ||
| amlogic/aml8726 | ||
| annapurna/alpine | ||
| arm | ||
| broadcom/bcm2835 | ||
| cloudabi32 | ||
| conf | ||
| freescale | ||
| include | ||
| linux | ||
| mv | ||
| nvidia | ||
| qemu | ||
| rockchip | ||
| samsung/exynos | ||
| ti | ||
| versatile | ||
| xilinx | ||