This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
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.. | ||
apb.c | ||
fire.c | ||
firereg.h | ||
firevar.h | ||
ofw_pci_if.m | ||
ofw_pci.h | ||
ofw_pcib_subr.c | ||
ofw_pcib_subr.h | ||
ofw_pcib.c | ||
ofw_pcibus.c | ||
psycho.c | ||
psychoreg.h | ||
psychovar.h | ||
sbbc.c | ||
schizo.c | ||
schizoreg.h | ||
schizovar.h |