971b5e4da8
This code caused more problems than it should have fixed (boot failures) on the machines I tested, so has been commented out for a while now. Remove it, and assume the errata fixups were done by the bootloader where they belong.
178 lines
5.8 KiB
C
178 lines
5.8 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (C) 2008 Semihalf, Rafal Jaworowski
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* Copyright 2006 by Juniper Networks.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MPC85XX_H_
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#define _MPC85XX_H_
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#include <machine/platformvar.h>
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/*
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* Configuration control and status registers
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*/
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extern vm_offset_t ccsrbar_va;
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extern vm_paddr_t ccsrbar_pa;
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extern vm_size_t ccsrbar_size;
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#define CCSRBAR_VA ccsrbar_va
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#define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0)
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#define OCP85XX_BPTR (CCSRBAR_VA + 0x20)
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#define OCP85XX_BSTRH (CCSRBAR_VA + 0x20)
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#define OCP85XX_BSTRL (CCSRBAR_VA + 0x24)
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#define OCP85XX_BSTAR (CCSRBAR_VA + 0x28)
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#define OCP85XX_COREDISR (CCSRBAR_VA + 0xE0094)
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#define OCP85XX_BRR (CCSRBAR_VA + 0xE00E4)
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/*
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* Run Control and Power Management registers
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*/
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#define CCSR_CTBENR (CCSRBAR_VA + 0xE2084)
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#define CCSR_CTBCKSELR (CCSRBAR_VA + 0xE208C)
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#define CCSR_CTBCHLTCR (CCSRBAR_VA + 0xE2094)
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/*
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* DDR Memory controller.
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*/
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#define OCP85XX_DDR1_CS0_CONFIG (CCSRBAR_VA + 0x8080)
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/*
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* E500 Coherency Module registers
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*/
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#define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010)
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/*
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* Local access registers
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*/
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/* Write order: OCP_LAWBARH -> OCP_LAWBARL -> OCP_LAWSR */
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#define OCP85XX_LAWBARH(n) (CCSRBAR_VA + 0xc00 + 0x10 * (n))
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#define OCP85XX_LAWBARL(n) (CCSRBAR_VA + 0xc04 + 0x10 * (n))
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#define OCP85XX_LAWSR_QORIQ(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n))
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#define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n))
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#define OCP85XX_LAWSR_85XX(n) (CCSRBAR_VA + 0xc10 + 0x10 * (n))
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#define OCP85XX_LAWSR(n) (mpc85xx_is_qoriq() ? OCP85XX_LAWSR_QORIQ(n) : \
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OCP85XX_LAWSR_85XX(n))
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/* Attribute register */
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#define OCP85XX_ENA_MASK 0x80000000
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#define OCP85XX_DIS_MASK 0x7fffffff
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#define OCP85XX_TGTIF_LBC_QORIQ 0x1f
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#define OCP85XX_TGTIF_RAM_INTL_QORIQ 0x14
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#define OCP85XX_TGTIF_RAM1_QORIQ 0x10
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#define OCP85XX_TGTIF_RAM2_QORIQ 0x11
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#define OCP85XX_TGTIF_BMAN 0x18
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#define OCP85XX_TGTIF_DCSR 0x1D
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#define OCP85XX_TGTIF_QMAN 0x3C
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#define OCP85XX_TRGT_SHIFT_QORIQ 20
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#define OCP85XX_TGTIF_LBC_85XX 0x04
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#define OCP85XX_TGTIF_RAM_INTL_85XX 0x0b
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#define OCP85XX_TGTIF_RIO_85XX 0x0c
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#define OCP85XX_TGTIF_RAM1_85XX 0x0f
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#define OCP85XX_TGTIF_RAM2_85XX 0x16
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#define OCP85XX_TGTIF_LBC \
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(mpc85xx_is_qoriq() ? OCP85XX_TGTIF_LBC_QORIQ : OCP85XX_TGTIF_LBC_85XX)
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#define OCP85XX_TGTIF_RAM_INTL \
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(mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM_INTL_QORIQ : OCP85XX_TGTIF_RAM_INTL_85XX)
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#define OCP85XX_TGTIF_RIO \
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(mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RIO_QORIQ : OCP85XX_TGTIF_RIO_85XX)
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#define OCP85XX_TGTIF_RAM1 \
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(mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM1_QORIQ : OCP85XX_TGTIF_RAM1_85XX)
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#define OCP85XX_TGTIF_RAM2 \
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(mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM2_QORIQ : OCP85XX_TGTIF_RAM2_85XX)
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/*
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* L2 cache registers
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*/
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#define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000)
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/*
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* L3 CoreNet platform cache (CPC) registers
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*/
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#define OCP85XX_CPC_CSR0 (CCSRBAR_VA + 0x10000)
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#define OCP85XX_CPC_CSR0_CE 0x80000000
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#define OCP85XX_CPC_CSR0_PE 0x40000000
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#define OCP85XX_CPC_CSR0_FI 0x00200000
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#define OCP85XX_CPC_CSR0_WT 0x00080000
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#define OCP85XX_CPC_CSR0_FL 0x00000800
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#define OCP85XX_CPC_CSR0_LFC 0x00000400
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#define OCP85XX_CPC_CFG0 (CCSRBAR_VA + 0x10008)
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#define OCP85XX_CPC_CFG_SZ_MASK 0x00003fff
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#define OCP85XX_CPC_CFG0_SZ_K(x) (((x) & OCP85XX_CPC_CFG_SZ_MASK) << 6)
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/*
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* Power-On Reset configuration
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*/
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#define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c)
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#define OCP85XX_PORDEVSR_IO_SEL 0x00780000
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#define OCP85XX_PORDEVSR_IO_SEL_SHIFT 19
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#define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014)
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/*
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* Status Registers.
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*/
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#define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0)
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#define OCP85XX_CLKDVDR (CCSRBAR_VA + 0xe0800)
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#define OCP85XX_CLKDVDR_PXCKEN 0x80000000
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#define OCP85XX_CLKDVDR_SSICKEN 0x20000000
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#define OCP85XX_CLKDVDR_PXCKINV 0x10000000
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#define OCP85XX_CLKDVDR_PXCLK_MASK 0x00FF0000
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#define OCP85XX_CLKDVDR_SSICLK_MASK 0x000000FF
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/*
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* Run Control/Power Management Registers.
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*/
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#define OCP85XX_RCPM_CDOZSR (CCSRBAR_VA + 0xe2004)
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#define OCP85XX_RCPM_CDOZCR (CCSRBAR_VA + 0xe200c)
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/*
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* Prototypes.
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*/
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uint32_t ccsr_read4(uintptr_t addr);
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void ccsr_write4(uintptr_t addr, uint32_t val);
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int law_enable(int trgt, uint64_t bar, uint32_t size);
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int law_disable(int trgt, uint64_t bar, uint32_t size);
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int law_getmax(void);
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int law_pci_target(struct resource *, int *, int *);
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DECLARE_CLASS(mpc85xx_platform);
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int mpc85xx_attach(platform_t);
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void mpc85xx_enable_l3_cache(void);
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int mpc85xx_is_qoriq(void);
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uint32_t mpc85xx_get_platform_clock(void);
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uint32_t mpc85xx_get_system_clock(void);
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#endif /* _MPC85XX_H_ */
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