aa0ea9d07a
MSI are implemented via software interrupt. PCIe cards will write into software interrupt register which will cause inbound shared interrupt which will be interpreted as a MSI. Obtained from: Marvell, Semihalf
81 lines
2.8 KiB
C
81 lines
2.8 KiB
C
/* $NetBSD: intr.h,v 1.7 2003/06/16 20:01:00 thorpej Exp $ */
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/*-
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* Copyright (c) 1997 Mark Brinicombe.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _MACHINE_INTR_H_
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#define _MACHINE_INTR_H_
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/* XXX move to std.* files? */
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#ifdef CPU_XSCALE_81342
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#define NIRQ 128
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#elif defined(CPU_XSCALE_PXA2X0)
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#include <arm/xscale/pxa/pxareg.h>
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#define NIRQ IRQ_GPIO_MAX
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#elif defined(SOC_MV_DISCOVERY)
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#define NIRQ 96
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#elif defined(CPU_ARM9) || defined(SOC_MV_KIRKWOOD) || \
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defined(CPU_XSCALE_IXP435)
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#define NIRQ 64
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#elif defined(CPU_CORTEXA)
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#define NIRQ 128
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#elif defined(CPU_ARM11)
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#define NIRQ 128
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#elif defined(SOC_MV_ARMADAXP)
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#define MAIN_IRQ_NUM 116
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#define ERR_IRQ_NUM 32
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#define ERR_IRQ (MAIN_IRQ_NUM)
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#define MSI_IRQ_NUM 32
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#define MSI_IRQ (ERR_IRQ + ERR_IRQ_NUM)
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#define NIRQ (MAIN_IRQ_NUM + ERR_IRQ_NUM + MSI_IRQ_NUM)
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#else
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#define NIRQ 32
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#endif
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#include <machine/psl.h>
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int arm_get_next_irq(int);
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void arm_mask_irq(uintptr_t);
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void arm_unmask_irq(uintptr_t);
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void arm_setup_irqhandler(const char *, int (*)(void*), void (*)(void*),
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void *, int, int, void **);
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int arm_remove_irqhandler(int, void *);
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extern void (*arm_post_filter)(void *);
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void gic_init_secondary(void);
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#endif /* _MACHINE_INTR_H */
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