Adrian Chadd 9a70a84852 The AR724x SoC's require the irq status line to be acked/cleared. ... This allows console IO to occur correctly once the kernel is in multi-user mode. Submitted by: Luiz Otavio O Souza		2011-04-30 12:07:15 +00:00
..
apb.c	The AR724x SoC's require the irq status line to be acked/cleared.	2011-04-30 12:07:15 +00:00
apbvar.h
ar71xx_bus_space_reversed.c
ar71xx_bus_space_reversed.h
ar71xx_chip.c	Add a missing DDR FIFO method for the ar71xx.	2011-04-30 02:31:56 +00:00
ar71xx_chip.h
ar71xx_cpudef.h	Tidy up the naming of the ip2 DDR flush routine, and add an inline	2011-04-29 06:25:11 +00:00
ar71xx_ehci.c	We don't need to call EOWRITE4(sc, EHCI_USBINTR, 0) directly from each EHCI	2011-04-12 07:49:11 +00:00
ar71xx_gpio.c
ar71xx_gpiovar.h
ar71xx_machdep.c	The previous commit didn't completely rename this to what it should be.	2011-03-28 09:10:59 +00:00
ar71xx_ohci.c
ar71xx_pci_bus_space.c
ar71xx_pci_bus_space.h
ar71xx_pci.c	Call the DDR FIFO flush method when IP2 interrupts occur.	2011-04-30 11:56:04 +00:00
ar71xx_setup.c
ar71xx_setup.h
ar71xx_spi.c
ar71xx_wdog.c
ar71xxreg.h
ar91xx_chip.c	Add the IP2 DDR flush handlers.	2011-04-28 11:13:26 +00:00
ar91xx_chip.h
ar91xxreg.h
ar724x_chip.c	Add the IP2 DDR flush handlers.	2011-04-28 11:13:26 +00:00
ar724x_chip.h
ar724x_pci.c	Flip off debugging for now.	2011-04-30 11:40:31 +00:00
ar724xreg.h	Add some initial PCIe bridge support for the AR724x chipsets.	2011-04-30 11:36:16 +00:00
files.ar71xx	Add some initial PCIe bridge support for the AR724x chipsets.	2011-04-30 11:36:16 +00:00
if_arge.c	if_arge has had a strange bug that only appears during high traffic	2011-04-05 06:46:07 +00:00
if_argevar.h	* Add some more debugging to if_arge	2011-04-05 06:33:35 +00:00
pcf2123_rtc.c
pcf2123reg.h
std.ar71xx
uart_bus_ar71xx.c
uart_cpu_ar71xx.c