614 lines
16 KiB
C
614 lines
16 KiB
C
/*-
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* Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
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* Copyright (c) 2011, Luiz Otavio O Souza.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/interrupt.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_extern.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr_machdep.h>
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#include <machine/pmap.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include "pcib_if.h"
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#include <mips/atheros/ar71xxreg.h>
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#include <mips/atheros/ar724xreg.h>
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#include <mips/atheros/ar71xx_setup.h>
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#include <mips/atheros/ar71xx_pci_bus_space.h> /* XXX */
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#include <mips/atheros/ar71xx_bus_space_reversed.h> /* XXX */
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#include <mips/atheros/ar71xx_cpudef.h>
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#undef AR724X_PCI_DEBUG
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#ifdef AR724X_PCI_DEBUG
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#define dprintf printf
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#else
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#define dprintf(x, arg...)
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#endif
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struct ar71xx_pci_softc {
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device_t sc_dev;
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int sc_busno;
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struct rman sc_mem_rman;
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struct rman sc_irq_rman;
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struct intr_event *sc_eventstab[AR71XX_PCI_NIRQS];
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mips_intrcnt_t sc_intr_counter[AR71XX_PCI_NIRQS];
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struct resource *sc_irq;
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void *sc_ih;
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};
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static int ar724x_pci_setup_intr(device_t, device_t, struct resource *, int,
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driver_filter_t *, driver_intr_t *, void *, void **);
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static int ar724x_pci_teardown_intr(device_t, device_t, struct resource *,
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void *);
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static int ar724x_pci_intr(void *);
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static void
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ar724x_pci_write(uint32_t reg, uint32_t offset, uint32_t data, int bytes)
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{
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uint32_t val, mask, shift;
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/* Register access is 32-bit aligned */
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shift = 8 * (offset & (bytes % 4));
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if (bytes % 4)
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mask = (1 << (bytes * 8)) - 1;
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else
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mask = 0xffffffff;
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val = ATH_READ_REG(reg + (offset & ~3));
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val &= ~(mask << shift);
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val |= ((data & mask) << shift);
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ATH_WRITE_REG(reg + (offset & ~3), val);
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dprintf("%s: %#x/%#x addr=%#x, data=%#x(%#x), bytes=%d\n", __func__,
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reg, reg + (offset & ~3), offset, data, val, bytes);
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}
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static uint32_t
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ar724x_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, int bytes)
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{
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uint32_t cmd, data, shift, mask;
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/* Register access is 32-bit aligned */
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shift = (reg & 3) * 8;
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if (shift)
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mask = (1 << shift) - 1;
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else
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mask = 0xffffffff;
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dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
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func, reg, bytes);
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if ((bus == 0) && (slot == 0) && (func == 0)) {
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data = ATH_READ_REG(AR724X_PCI_CFG_BASE + (reg & ~3));
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/*
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* WAR for BAR issue - We are unable to access the PCI device
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* space if we set the BAR with proper base address.
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*/
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if (reg == PCIR_BAR(0) && bytes == 4) {
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cmd = (ar71xx_soc == AR71XX_SOC_AR7240) ?
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0xffff : 0x1000ffff;
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ar724x_pci_write(AR724X_PCI_CFG_BASE, reg, cmd, bytes);
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}
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} else
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data = -1;
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/* Get request bytes from 32-bit word */
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data = (data >> shift) & mask;
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dprintf("%s: read 0x%x\n", __func__, data);
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return (data);
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}
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static void
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ar724x_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, uint32_t data, int bytes)
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{
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dprintf("%s: tag (%x, %x, %x) reg %d(%d): %x\n", __func__, bus, slot,
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func, reg, bytes, data);
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if ((bus != 0) || (slot != 0) || (func != 0))
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return;
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ar724x_pci_write(AR724X_PCI_CFG_BASE, reg, data, bytes);
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/*
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* WAR for BAR issue - We are unable to access the PCI device space
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* if we set the BAR with proper base address.
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* Force a flush here (at register writing).
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*/
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if (reg == PCIR_BAR(0) && bytes == 4)
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(void)ar724x_pci_read_config(dev, bus, slot, func, reg, bytes);
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}
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static void
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ar724x_pci_mask_irq(void *source)
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{
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uint32_t reg;
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unsigned int irq = (unsigned int)source;
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/* XXX - Only one interrupt ? Only one device ? */
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if (irq != AR71XX_PCI_IRQ_START)
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return;
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/* Update the interrupt mask reg */
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reg = ATH_READ_REG(AR724X_PCI_INTR_MASK);
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ATH_WRITE_REG(AR724X_PCI_INTR_MASK,
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reg & ~AR724X_PCI_INTR_DEV0);
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/* Clear any pending interrupt */
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reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS);
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ATH_WRITE_REG(AR724X_PCI_INTR_STATUS,
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reg | AR724X_PCI_INTR_DEV0);
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}
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static void
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ar724x_pci_unmask_irq(void *source)
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{
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uint32_t reg;
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unsigned int irq = (unsigned int)source;
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/* XXX */
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if (irq != AR71XX_PCI_IRQ_START)
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return;
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/* Update the interrupt mask reg */
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reg = ATH_READ_REG(AR724X_PCI_INTR_MASK);
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ATH_WRITE_REG(AR724X_PCI_INTR_MASK,
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reg | AR724X_PCI_INTR_DEV0);
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}
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static int
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ar724x_pci_setup(device_t dev)
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{
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uint32_t reg;
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/* setup COMMAND register */
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reg = PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_SERRESPEN |
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PCIM_CMD_BACKTOBACK | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN;
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ar724x_pci_write(AR724X_PCI_CRP_BASE, PCIR_COMMAND, reg, 2);
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ar724x_pci_write(AR724X_PCI_CRP_BASE, 0x20, 0x1ff01000, 4);
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ar724x_pci_write(AR724X_PCI_CRP_BASE, 0x24, 0x1ff01000, 4);
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reg = ATH_READ_REG(AR724X_PCI_RESET);
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if (reg != 0x7) {
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DELAY(100000);
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ATH_WRITE_REG(AR724X_PCI_RESET, 0);
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DELAY(100);
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ATH_WRITE_REG(AR724X_PCI_RESET, 4);
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DELAY(100000);
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}
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if (ar71xx_soc == AR71XX_SOC_AR7240)
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reg = AR724X_PCI_APP_LTSSM_ENABLE;
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else
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reg = 0x1ffc1;
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ATH_WRITE_REG(AR724X_PCI_APP, reg);
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DELAY(1000);
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reg = ATH_READ_REG(AR724X_PCI_RESET);
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if ((reg & AR724X_PCI_RESET_LINK_UP) == 0) {
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device_printf(dev, "no PCIe controller found\n");
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return (ENXIO);
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}
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if (ar71xx_soc == AR71XX_SOC_AR7241 ||
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ar71xx_soc == AR71XX_SOC_AR7242) {
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reg = ATH_READ_REG(AR724X_PCI_APP);
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reg |= (1 << 16);
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ATH_WRITE_REG(AR724X_PCI_APP, reg);
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}
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return (0);
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}
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#define AR5416_EEPROM_MAGIC 0xa55a
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/*
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* XXX - This should not be here ! And this looks like Atheros (if_ath) only.
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*/
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static void
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ar724x_load_eeprom_data(device_t dev)
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{
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uint32_t bar0, hint, reg, val;
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uint16_t *data = NULL;
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/* Search for a hint of eeprom data offset */
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if (resource_int_value(device_get_name(dev),
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device_get_unit(dev), "eepromdata", &hint) != 0)
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return;
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device_printf(dev, "Loading the eeprom fixup data from %#x\n", hint);
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data = (uint16_t *)MIPS_PHYS_TO_KSEG1(hint);
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if (*data != AR5416_EEPROM_MAGIC) {
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device_printf(dev, "Invalid calibration data from %#x\n", hint);
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return;
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}
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/* Save bar(0) address - just to flush bar(0) (SoC WAR) ? */
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bar0 = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_BAR(0), 4);
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val = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_COMMAND, 2);
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val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
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ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, val, 2);
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/* set pointer to first reg address */
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data += 3;
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while (*data != 0xffff) {
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reg = *data++;
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val = *data++;
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val |= (*data++) << 16;
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/* Write eeprom fixup data to device memory */
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ATH_WRITE_REG(AR71XX_PCI_MEM_BASE + reg, val);
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DELAY(100);
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}
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val = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_COMMAND, 2);
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val &= ~(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
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ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, val, 2);
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/* Write the saved bar(0) address */
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ar724x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0), bar0, 4);
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}
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#undef AR5416_EEPROM_MAGIC
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static int
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ar724x_pci_probe(device_t dev)
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{
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return (0);
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}
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static int
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ar724x_pci_attach(device_t dev)
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{
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struct ar71xx_pci_softc *sc = device_get_softc(dev);
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int busno = 0;
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int rid = 0;
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sc->sc_mem_rman.rm_type = RMAN_ARRAY;
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sc->sc_mem_rman.rm_descr = "ar724x PCI memory window";
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if (rman_init(&sc->sc_mem_rman) != 0 ||
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rman_manage_region(&sc->sc_mem_rman, AR71XX_PCI_MEM_BASE,
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AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1) != 0) {
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panic("ar724x_pci_attach: failed to set up I/O rman");
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}
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sc->sc_irq_rman.rm_type = RMAN_ARRAY;
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sc->sc_irq_rman.rm_descr = "ar724x PCI IRQs";
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if (rman_init(&sc->sc_irq_rman) != 0 ||
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rman_manage_region(&sc->sc_irq_rman, AR71XX_PCI_IRQ_START,
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AR71XX_PCI_IRQ_END) != 0)
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panic("ar724x_pci_attach: failed to set up IRQ rman");
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/* Disable interrupts */
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ATH_WRITE_REG(AR724X_PCI_INTR_STATUS, 0);
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ATH_WRITE_REG(AR724X_PCI_INTR_MASK, 0);
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/* Hook up our interrupt handler. */
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if ((sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_SHAREABLE | RF_ACTIVE)) == NULL) {
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device_printf(dev, "unable to allocate IRQ resource\n");
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return (ENXIO);
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}
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if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
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ar724x_pci_intr, NULL, sc, &sc->sc_ih))) {
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device_printf(dev,
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"WARNING: unable to register interrupt handler\n");
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return (ENXIO);
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}
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/* Reset PCIe core and PCIe PHY */
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ar71xx_device_stop(AR724X_RESET_PCIE);
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ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
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ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
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DELAY(100);
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ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
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DELAY(100);
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ar71xx_device_start(AR724X_RESET_PCIE_PHY);
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ar71xx_device_start(AR724X_RESET_PCIE);
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if (ar724x_pci_setup(dev))
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return (ENXIO);
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/* XXX - Load eeprom fixup data */
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ar724x_load_eeprom_data(dev);
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/* Fixup internal PCI bridge */
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ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND,
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PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN
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| PCIM_CMD_SERRESPEN | PCIM_CMD_BACKTOBACK
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| PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN, 2);
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device_add_child(dev, "pci", busno);
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return (bus_generic_attach(dev));
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}
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static int
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ar724x_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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struct ar71xx_pci_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_DOMAIN:
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*result = 0;
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return (0);
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case PCIB_IVAR_BUS:
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*result = sc->sc_busno;
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return (0);
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}
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return (ENOENT);
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}
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static int
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ar724x_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
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{
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struct ar71xx_pci_softc * sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_BUS:
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sc->sc_busno = result;
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return (0);
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}
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return (ENOENT);
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}
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static struct resource *
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ar724x_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct ar71xx_pci_softc *sc = device_get_softc(bus);
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struct resource *rv;
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struct rman *rm;
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switch (type) {
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case SYS_RES_IRQ:
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rm = &sc->sc_irq_rman;
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break;
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case SYS_RES_MEMORY:
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rm = &sc->sc_mem_rman;
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break;
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default:
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return (NULL);
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}
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rv = rman_reserve_resource(rm, start, end, count, flags, child);
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if (rv == NULL)
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return (NULL);
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rman_set_rid(rv, *rid);
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if (flags & RF_ACTIVE) {
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if (bus_activate_resource(child, type, *rid, rv)) {
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rman_release_resource(rv);
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return (NULL);
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}
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}
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return (rv);
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}
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static int
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ar724x_pci_activate_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
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child, type, rid, r));
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if (!res) {
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switch(type) {
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case SYS_RES_MEMORY:
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case SYS_RES_IOPORT:
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/* XXX */
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//rman_set_bustag(r, ar71xx_bus_space_pcimem);
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//rman_set_bustag(r, mips_bus_space_generic);
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rman_set_bustag(r, ar71xx_bus_space_reversed);
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break;
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}
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}
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return (res);
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}
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static int
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ar724x_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
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int flags, driver_filter_t *filt, driver_intr_t *handler,
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void *arg, void **cookiep)
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{
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struct ar71xx_pci_softc *sc = device_get_softc(bus);
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struct intr_event *event;
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int irq, error;
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irq = rman_get_start(ires);
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if (irq > AR71XX_PCI_IRQ_END)
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panic("%s: bad irq %d", __func__, irq);
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event = sc->sc_eventstab[irq];
|
|
if (event == NULL) {
|
|
error = intr_event_create(&event, (void *)irq, 0, irq,
|
|
ar724x_pci_mask_irq, ar724x_pci_unmask_irq, NULL, NULL,
|
|
"pci intr%d:", irq);
|
|
|
|
if (error == 0) {
|
|
sc->sc_eventstab[irq] = event;
|
|
sc->sc_intr_counter[irq] =
|
|
mips_intrcnt_create(event->ie_name);
|
|
}
|
|
else
|
|
return error;
|
|
}
|
|
|
|
intr_event_add_handler(event, device_get_nameunit(child), filt,
|
|
handler, arg, intr_priority(flags), flags, cookiep);
|
|
mips_intrcnt_setname(sc->sc_intr_counter[irq], event->ie_fullname);
|
|
|
|
ar724x_pci_unmask_irq((void*)irq);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ar724x_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
|
|
void *cookie)
|
|
{
|
|
struct ar71xx_pci_softc *sc = device_get_softc(dev);
|
|
int irq, result;
|
|
|
|
irq = rman_get_start(ires);
|
|
if (irq > AR71XX_PCI_IRQ_END)
|
|
panic("%s: bad irq %d", __func__, irq);
|
|
|
|
if (sc->sc_eventstab[irq] == NULL)
|
|
panic("Trying to teardown unoccupied IRQ");
|
|
|
|
ar724x_pci_mask_irq((void*)irq);
|
|
|
|
result = intr_event_remove_handler(cookie);
|
|
if (!result)
|
|
sc->sc_eventstab[irq] = NULL;
|
|
|
|
return (result);
|
|
}
|
|
|
|
static int
|
|
ar724x_pci_intr(void *arg)
|
|
{
|
|
struct ar71xx_pci_softc *sc = arg;
|
|
struct intr_event *event;
|
|
uint32_t reg, irq, mask;
|
|
|
|
ar71xx_device_ddr_flush_ip2();
|
|
|
|
reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS);
|
|
mask = ATH_READ_REG(AR724X_PCI_INTR_MASK);
|
|
/*
|
|
* Handle only unmasked interrupts
|
|
*/
|
|
reg &= mask;
|
|
if (reg & AR724X_PCI_INTR_DEV0) {
|
|
|
|
irq = AR71XX_PCI_IRQ_START;
|
|
event = sc->sc_eventstab[irq];
|
|
if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
|
|
printf("Stray IRQ %d\n", irq);
|
|
return (FILTER_STRAY);
|
|
}
|
|
|
|
/* TODO: frame instead of NULL? */
|
|
intr_event_handle(event, NULL);
|
|
mips_intrcnt_inc(sc->sc_intr_counter[irq]);
|
|
}
|
|
|
|
return (FILTER_HANDLED);
|
|
}
|
|
|
|
static int
|
|
ar724x_pci_maxslots(device_t dev)
|
|
{
|
|
|
|
return (PCI_SLOTMAX);
|
|
}
|
|
|
|
static int
|
|
ar724x_pci_route_interrupt(device_t pcib, device_t device, int pin)
|
|
{
|
|
|
|
return (pci_get_slot(device));
|
|
}
|
|
|
|
static device_method_t ar724x_pci_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, ar724x_pci_probe),
|
|
DEVMETHOD(device_attach, ar724x_pci_attach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_print_child, bus_generic_print_child),
|
|
DEVMETHOD(bus_read_ivar, ar724x_pci_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, ar724x_pci_write_ivar),
|
|
DEVMETHOD(bus_alloc_resource, ar724x_pci_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
|
DEVMETHOD(bus_activate_resource, ar724x_pci_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, ar724x_pci_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, ar724x_pci_teardown_intr),
|
|
|
|
/* pcib interface */
|
|
DEVMETHOD(pcib_maxslots, ar724x_pci_maxslots),
|
|
DEVMETHOD(pcib_read_config, ar724x_pci_read_config),
|
|
DEVMETHOD(pcib_write_config, ar724x_pci_write_config),
|
|
DEVMETHOD(pcib_route_interrupt, ar724x_pci_route_interrupt),
|
|
|
|
{0, 0}
|
|
};
|
|
|
|
static driver_t ar724x_pci_driver = {
|
|
"pcib",
|
|
ar724x_pci_methods,
|
|
sizeof(struct ar71xx_pci_softc),
|
|
};
|
|
|
|
static devclass_t ar724x_pci_devclass;
|
|
|
|
DRIVER_MODULE(ar724x_pci, nexus, ar724x_pci_driver, ar724x_pci_devclass, 0, 0);
|