Neel Natu b5b28fc9dc Add support for level triggered interrupt pins on the vioapic. Prior to this ... commit level triggered interrupts would work as long as the pin was not shared among multiple interrupt sources. The vlapic now keeps track of level triggered interrupts in the trigger mode register and will forward the EOI for a level triggered interrupt to the vioapic. The vioapic in turn uses the EOI to sample the level on the pin and re-inject the vector if the pin is still asserted. The vhpet is the first consumer of level triggered interrupts and advertises that it can generate interrupts on pins 20 through 23 of the vioapic. Discussed with: grehan@		2013-11-27 22:18:08 +00:00
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acpica	Consistently use round_page(x) rather than roundup(x, PAGE_SIZE). There is	2013-02-15 22:43:08 +00:00
amd64	- For kernel compiled only with KDTRACE_HOOKS and not any lock debugging	2013-11-25 07:38:45 +00:00
conf	Include XEN and HyperV into amd64 LINT.	2013-10-28 21:11:28 +00:00
ia32	x86: Allow users to change PSL_RF via ptrace(PT_SETREGS...)	2013-11-14 15:37:20 +00:00
include	Hide struct pcb definition by #ifdef __amd64__ braces. If cc -m32	2013-11-26 19:38:42 +00:00
linux32	- For kernel compiled only with KDTRACE_HOOKS and not any lock debugging	2013-11-25 07:38:45 +00:00
pci	Remove duplicate code. Reduce diff between amd64 and i386.	2012-12-01 00:56:19 +00:00
vmm	Add support for level triggered interrupt pins on the vioapic. Prior to this	2013-11-27 22:18:08 +00:00
Makefile