60 lines
1.7 KiB
Plaintext
60 lines
1.7 KiB
Plaintext
/*
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* at91sama5d3_mci2.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
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* 3 MMC ports
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*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* Licensed under GPLv2.
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*/
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/at91.h>
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/ {
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ahb {
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apb {
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pinctrl@fffff200 {
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mmc2 {
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pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
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atmel,pins =
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<AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A MCI2_CK, conflicts with PCK2 */
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AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC10 periph A MCI2_CDA with pullup */
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AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC11 periph A MCI2_DA0 with pullup */
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};
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pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
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atmel,pins =
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<AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
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AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
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AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
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};
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};
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};
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pmc: pmc@fffffc00 {
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periphck {
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mci2_clk: mci2_clk {
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#clock-cells = <0>;
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reg = <23>;
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};
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};
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};
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mmc2: mmc@f8004000 {
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compatible = "atmel,hsmci";
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reg = <0xf8004000 0x600>;
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interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
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dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
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dma-names = "rxtx";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
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clocks = <&mci2_clk>;
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clock-names = "mci_clk";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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};
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