Konstantin Belousov e44f4f3547 mlx5en: Avoid SFENCe on x86 ... The IA32 memory model guarantees that all writes are seen in the program order. Also, any access to the uncacheable memory flushes the store buffers. As the consequence, SFENCE instruction is (almost) never needed, in particular, it is not needed to ensure the correct order of updates as seen by a PCIe device. Use atomic_thread_fence_rel() instead of wb() to only emit compiler barriers on x86 there. Other architectures get the right barrier instruction as well. Reviewed by: hselasky Sponsored by: Mellanox Technologies MFC after: 1 week		2017-12-19 14:11:41 +00:00
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mlx5_core	Remove duplicate static function prototype to fix compilation of	2017-11-18 20:32:09 +00:00
mlx5_en	mlx5en: Avoid SFENCe on x86	2017-12-19 14:11:41 +00:00
mlx5_ib	Compile fixes for 32-bit architectures.	2017-11-24 12:08:50 +00:00
cq.h
device.h	Implement hardware mlx5(4) rx timestamps.	2017-11-29 10:04:11 +00:00
diagnostics.h
doorbell.h
driver.h	Add more and update existing mlx5 core firmware structure definitions and bits.	2017-11-10 14:39:03 +00:00
fs.h	Refactor the flowsteering APIs used by mlx5en(4). This change is needed by	2017-11-10 09:49:08 +00:00
mlx5_ifc.h	Add more and update existing mlx5 core firmware structure definitions and bits.	2017-11-10 14:39:03 +00:00
mlx5_rdma_if.h
qp.h	The new mlx5ib(4) module requires some existing values to be redefined.	2017-11-10 15:28:17 +00:00
srq.h
vport.h	Add API function to query port performance counters for infiniband and RoCE	2017-11-10 13:58:49 +00:00