dc4ee6ca91
make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
186 lines
8.5 KiB
C
186 lines
8.5 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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* Definitions for enumerations used with Octeon CSRs.
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*
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* <hr>$Revision: 70030 $<hr>
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*
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*/
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#ifndef __CVMX_CSR_ENUMS_H__
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#define __CVMX_CSR_ENUMS_H__
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typedef enum {
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CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */
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CVMX_IPD_OPC_MODE_STF = 1LL, /* All blocks into L2 */
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CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */
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CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */
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} cvmx_ipd_mode_t;
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/**
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* Enumeration representing the amount of packet processing
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* and validation performed by the input hardware.
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*/
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typedef enum
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{
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CVMX_PIP_PORT_CFG_MODE_NONE = 0ull, /**< Packet input doesn't perform any
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processing of the input packet. */
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CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,/**< Full packet processing is performed
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with pointer starting at the L2
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(ethernet MAC) header. */
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CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull /**< Input packets are assumed to be IP.
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Results from non IP packets is
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undefined. Pointers reference the
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beginning of the IP header. */
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} cvmx_pip_port_parse_mode_t;
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/**
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* This enumeration controls how a QoS watcher matches a packet.
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*
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* @deprecated This enumeration was used with cvmx_pip_config_watcher which has
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* been deprecated.
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*/
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typedef enum
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{
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CVMX_PIP_QOS_WATCH_DISABLE = 0ull, /**< QoS watcher is diabled */
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CVMX_PIP_QOS_WATCH_PROTNH = 1ull, /**< QoS watcher will match based on the IP protocol */
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CVMX_PIP_QOS_WATCH_TCP = 2ull, /**< QoS watcher will match TCP packets to a specific destination port */
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CVMX_PIP_QOS_WATCH_UDP = 3ull /**< QoS watcher will match UDP packets to a specific destination port */
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} cvmx_pip_qos_watch_types;
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/**
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* This enumeration is used in PIP tag config to control how
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* POW tags are generated by the hardware.
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*/
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typedef enum
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{
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CVMX_PIP_TAG_MODE_TUPLE = 0ull, /**< Always use tuple tag algorithm. This is the only mode supported on Pass 1 */
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CVMX_PIP_TAG_MODE_MASK = 1ull, /**< Always use mask tag algorithm */
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CVMX_PIP_TAG_MODE_IP_OR_MASK = 2ull, /**< If packet is IP, use tuple else use mask */
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CVMX_PIP_TAG_MODE_TUPLE_XOR_MASK = 3ull /**< tuple XOR mask */
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} cvmx_pip_tag_mode_t;
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/**
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* Tag type definitions
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*/
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typedef enum
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{
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CVMX_POW_TAG_TYPE_ORDERED = 0L, /**< Tag ordering is maintained */
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CVMX_POW_TAG_TYPE_ATOMIC = 1L, /**< Tag ordering is maintained, and at most one PP has the tag */
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CVMX_POW_TAG_TYPE_NULL = 2L, /**< The work queue entry from the order
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- NEVER tag switch from NULL to NULL */
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CVMX_POW_TAG_TYPE_NULL_NULL = 3L /**< A tag switch to NULL, and there is no space reserved in POW
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- NEVER tag switch to NULL_NULL
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- NEVER tag switch from NULL_NULL
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- NULL_NULL is entered at the beginning of time and on a deschedule.
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- NULL_NULL can be exited by a new work request. A NULL_SWITCH load can also switch the state to NULL */
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} cvmx_pow_tag_type_t;
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/**
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* LCR bits 0 and 1 control the number of bits per character. See the following table for encodings:
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*
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* - 00 = 5 bits (bits 0-4 sent)
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* - 01 = 6 bits (bits 0-5 sent)
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* - 10 = 7 bits (bits 0-6 sent)
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* - 11 = 8 bits (all bits sent)
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*/
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typedef enum
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{
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CVMX_UART_BITS5 = 0,
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CVMX_UART_BITS6 = 1,
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CVMX_UART_BITS7 = 2,
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CVMX_UART_BITS8 = 3
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} cvmx_uart_bits_t;
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/**
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* Interrupt Priority Interrupt Interrupt Interrupt
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* ID Level Type Source Reset By
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* ---------------------------------------------------------------------------------------------------------------------------------
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* 0001 - None None -
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*
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* 0110 Highest Receiver Line Overrun, parity, or framing errors or break Reading the Line Status Register
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* Status interrupt
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*
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* 0100 Second Received Data Receiver data available (FIFOs disabled) or Reading the Receiver Buffer Register
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* Available RX FIFO trigger level reached (FIFOs (FIFOs disabled) or the FIFO drops below
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* enabled) the trigger level (FIFOs enabled)
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*
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* 1100 Second Character No characters in or out of the RX FIFO Reading the Receiver Buffer Register
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* Timeout during the last 4 character times and there
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* Indication is at least 1 character in it during this
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* time
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*
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* 0010 Third Transmitter Transmitter Holding Register Empty Reading the Interrupt Identity Register
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* Holding (Programmable THRE Mode disabled) or TX (if source of interrupt) or writing into
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* Register FIFO at or below threshold (Programmable THR (FIFOs or THRE Mode disabled) or TX
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* Empty THRE Mode enabled) FIFO above threshold (FIFOs and THRE
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* Mode enabled)
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*
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* 0000 Fourth Modem Status Clear To Send (CTS) or Data Set Ready (DSR) Reading the Modem Status Register
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* Changed or Ring Indicator (RI) or Data Center
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* Detect (DCD) changed
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*
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* 0111 Fifth Busy Detect Software has tried to write to the Line Reading the UART Status Register
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* Indication Control Register while the BUSY bit of the
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* UART Status Register was set
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*/
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typedef enum
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{
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CVMX_UART_IID_NONE = 1,
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CVMX_UART_IID_RX_ERROR = 6,
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CVMX_UART_IID_RX_DATA = 4,
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CVMX_UART_IID_RX_TIMEOUT = 12,
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CVMX_UART_IID_TX_EMPTY = 2,
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CVMX_UART_IID_MODEM = 0,
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CVMX_UART_IID_BUSY = 7
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} cvmx_uart_iid_t;
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#endif /* __CVMX_CSR_ENUMS_H__ */
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