Intel Stratix 10 SoC includes a quad-core arm64 cluster and FPGA fabric. This adds support for reconfiguring FPGA. Accessing FPGA core of this SoC require the level of privilege EL3, while kernel runs in EL1 (lower) level of privilege. This provides an Intel service layer interface that uses SMCCC to pass queries to the secure-monitor (EL3). Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D21454
100 lines
4.2 KiB
C
100 lines
4.2 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory (Department of Computer Science and
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* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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* DARPA SSITH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ARM64_INTEL_INTEL_SMC_H_
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#define _ARM64_INTEL_INTEL_SMC_H_
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#include <dev/psci/smccc.h>
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/*
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* Intel SiP return values.
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*/
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#define INTEL_SIP_SMC_STATUS_OK 0
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#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY 1
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#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED 2
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#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR 4
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#define INTEL_SIP_SMC_REG_ERROR 5
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#define INTEL_SIP_SMC_RSU_ERROR 7
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/*
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* Intel SiP calls.
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*/
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#define INTEL_SIP_SMC_STD_CALL(func) \
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SMCCC_FUNC_ID(SMCCC_YIELDING_CALL, SMCCC_64BIT_CALL, \
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SMCCC_SIP_SERVICE_CALLS, (func))
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#define INTEL_SIP_SMC_FAST_CALL(func) \
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SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_64BIT_CALL, \
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SMCCC_SIP_SERVICE_CALLS, (func))
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#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1
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#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2
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#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3
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#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4
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#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5
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#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6
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#define INTEL_SIP_SMC_FUNCID_REG_READ 7
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#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8
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#define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9
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#define INTEL_SIP_SMC_FUNCID_RSU_STATUS 11
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#define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12
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#define INTEL_SIP_SMC_FPGA_CONFIG_START \
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INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START)
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#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \
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INTEL_SIP_SMC_STD_CALL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE)
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#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \
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INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
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#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \
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INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE)
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#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \
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INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM)
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#define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \
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INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK)
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#define INTEL_SIP_SMC_REG_READ \
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INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_REG_READ)
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#define INTEL_SIP_SMC_REG_WRITE \
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INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
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#define INTEL_SIP_SMC_REG_UPDATE \
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INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_REG_UPDATE)
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#define INTEL_SIP_SMC_RSU_STATUS \
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INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_RSU_STATUS)
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#define INTEL_SIP_SMC_RSU_UPDATE \
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INTEL_SIP_SMC_FAST_CALL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE)
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typedef int (*intel_smc_callfn_t)(register_t, register_t, register_t,
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register_t, register_t, register_t, register_t, register_t,
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struct arm_smccc_res *res);
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#endif /* _ARM64_INTEL_INTEL_SMC_H_ */
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