dc4ee6ca91
make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
392 lines
12 KiB
C
392 lines
12 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* interface to the low latency DRAM
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*
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* <hr>$Revision: 70030 $<hr>
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*
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*/
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#ifndef __CVMX_LLM_H__
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#define __CVMX_LLM_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define ENABLE_DEPRECATED /* Set to enable the old 18/36 bit names */
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typedef enum
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{
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CVMX_LLM_REPLICATION_NONE = 0,
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CVMX_LLM_REPLICATION_2X = 1, // on both interfaces, or 2x if only one interface
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CVMX_LLM_REPLICATION_4X = 2, // both interfaces, 2x, or 4x if only one interface
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CVMX_LLM_REPLICATION_8X = 3, // both interfaces, 4x, or 8x if only one interface
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} cvmx_llm_replication_t;
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/**
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* This structure defines the address used to the low-latency memory.
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* This address format is used for both loads and stores.
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*/
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typedef union
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{
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uint64_t u64;
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struct
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{
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uint64_t mbz :30;
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cvmx_llm_replication_t repl : 2;
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uint64_t address :32; // address<1:0> mbz, address<31:30> mbz
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} s;
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} cvmx_llm_address_t;
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/**
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* This structure defines the data format in the low-latency memory
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*/
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typedef union
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{
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uint64_t u64;
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/**
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* this format defines the format returned on a load
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* a load returns the 32/36-bits in memory, plus xxor = even_parity(dat<35:0>)
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* typically, dat<35> = parity(dat<34:0>), so the xor bit directly indicates parity error
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* Note that the data field size is 36 bits on the 36XX/38XX, and 32 bits on the 31XX
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*/
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struct
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{
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uint64_t mbz1 :27;
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uint64_t xxor : 1;
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uint64_t mbz : 4;
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uint64_t dat :32;
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} cn31xx;
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struct
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{
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uint64_t mbz :27;
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uint64_t xxor : 1;
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uint64_t dat :36;
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} s;
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/**
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* This format defines what should be used if parity is desired. Hardware returns
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* the XOR of all the bits in the 36/32 bit data word, so for parity software must use
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* one of the data field bits as a parity bit.
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*/
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struct cn31xx_par_struct
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{
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uint64_t mbz :32;
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uint64_t par : 1;
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uint64_t dat :31;
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} cn31xx_par;
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struct cn38xx_par_struct
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{
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uint64_t mbz :28;
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uint64_t par : 1;
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uint64_t dat :35;
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} cn38xx_par;
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#if !OCTEON_IS_COMMON_BINARY()
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#if CVMX_COMPILED_FOR(OCTEON_CN31XX)
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struct cn31xx_par_struct spar;
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#else
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struct cn38xx_par_struct spar;
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#endif
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#endif
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} cvmx_llm_data_t;
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#define CVMX_LLM_NARROW_DATA_WIDTH ((CVMX_COMPILED_FOR(OCTEON_CN31XX)) ? 32 : 36)
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/**
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* Calculate the parity value of a number
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*
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* @param value
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* @return parity value
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*/
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static inline uint64_t cvmx_llm_parity(uint64_t value)
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{
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uint64_t result;
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CVMX_DPOP(result, value);
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return result;
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}
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/**
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* Calculate the ECC needed for 36b LLM mode
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*
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* @param value
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* @return ECC value
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*/
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static inline int cvmx_llm_ecc(uint64_t value)
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{
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/* FIXME: This needs a re-write */
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static const uint32_t ecc_code_29[7] = {
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0x08962595,
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0x112a4aaa,
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0x024c934f,
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0x04711c73,
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0x0781e07c,
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0x1801ff80,
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0x1ffe0000};
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uint64_t pop0, pop1, pop2, pop3, pop4, pop5, pop6;
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pop0 = ecc_code_29[0];
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pop1 = ecc_code_29[1];
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pop2 = ecc_code_29[2];
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pop0 &= value;
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pop3 = ecc_code_29[3];
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CVMX_DPOP(pop0, pop0);
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pop4 = ecc_code_29[4];
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pop1 &= value;
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CVMX_DPOP(pop1, pop1);
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pop2 &= value;
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pop5 = ecc_code_29[5];
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CVMX_DPOP(pop2, pop2);
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pop6 = ecc_code_29[6];
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pop3 &= value;
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CVMX_DPOP(pop3, pop3);
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pop4 &= value;
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CVMX_DPOP(pop4, pop4);
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pop5 &= value;
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CVMX_DPOP(pop5, pop5);
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pop6 &= value;
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CVMX_DPOP(pop6, pop6);
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return((pop6&1)<<6) | ((pop5&1)<<5) | ((pop4&1)<<4) | ((pop3&1)<<3) | ((pop2&1)<<2) | ((pop1&1)<<1) | (pop0&1);
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}
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#ifdef ENABLE_DEPRECATED
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/* These macros are provided to provide compatibility with code that uses
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** the old names for the llm access functions. The names were changed
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** when support for the 31XX llm was added, as the widths differ between Octeon Models.
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** The wide/narrow names are preferred, and should be used in all new code */
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#define cvmx_llm_write36 cvmx_llm_write_narrow
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#define cvmx_llm_read36 cvmx_llm_read_narrow
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#define cvmx_llm_write64 cvmx_llm_write_wide
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#define cvmx_llm_read64 cvmx_llm_read_wide
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#endif
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/**
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* Write to LLM memory - 36 bit
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*
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* @param address Address in LLM to write. Consecutive writes increment the
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* address by 4. The replication mode is also encoded in this
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* address.
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* @param value Value to write to LLM. Only the low 36 bits will be used.
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* @param set Which of the two coprocessor 2 register sets to use for the
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* write. May be used to get two outstanding LLM access at once
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* per core. Range: 0-1
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*/
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static inline void cvmx_llm_write_narrow(cvmx_llm_address_t address, uint64_t value, int set)
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{
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cvmx_llm_data_t data;
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data.s.mbz = 0;
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data.s.dat = value;
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data.s.xxor = 0;
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if (set)
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{
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CVMX_MT_LLM_DATA(1, data.u64);
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CVMX_MT_LLM_WRITE_ADDR_INTERNAL(1, address.u64);
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}
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else
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{
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CVMX_MT_LLM_DATA(0, data.u64);
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CVMX_MT_LLM_WRITE_ADDR_INTERNAL(0, address.u64);
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}
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}
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/**
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* Write to LLM memory - 64 bit
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*
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* @param address Address in LLM to write. Consecutive writes increment the
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* address by 8. The replication mode is also encoded in this
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* address.
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* @param value Value to write to LLM.
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* @param set Which of the two coprocessor 2 register sets to use for the
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* write. May be used to get two outstanding LLM access at once
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* per core. Range: 0-1
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*/
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static inline void cvmx_llm_write_wide(cvmx_llm_address_t address, uint64_t value, int set)
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{
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if (set)
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{
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CVMX_MT_LLM_DATA(1, value);
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CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(1, address.u64);
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}
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else
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{
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CVMX_MT_LLM_DATA(0, value);
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CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(0, address.u64);
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}
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}
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/**
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* Read from LLM memory - 36 bit
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*
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* @param address Address in LLM to read. Consecutive reads increment the
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* address by 4. The replication mode is also encoded in this
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* address.
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* @param set Which of the two coprocessor 2 register sets to use for the
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* write. May be used to get two outstanding LLM access at once
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* per core. Range: 0-1
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* @return The lower 36 bits contain the result of the read
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*/
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static inline cvmx_llm_data_t cvmx_llm_read_narrow(cvmx_llm_address_t address, int set)
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{
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cvmx_llm_data_t value;
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if (set)
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{
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CVMX_MT_LLM_READ_ADDR(1, address.u64);
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CVMX_MF_LLM_DATA(1, value.u64);
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}
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else
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{
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CVMX_MT_LLM_READ_ADDR(0, address.u64);
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CVMX_MF_LLM_DATA(0, value.u64);
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}
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return value;
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}
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/**
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* Read from LLM memory - 64 bit
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*
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* @param address Address in LLM to read. Consecutive reads increment the
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* address by 8. The replication mode is also encoded in this
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* address.
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* @param set Which of the two coprocessor 2 register sets to use for the
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* write. May be used to get two outstanding LLM access at once
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* per core. Range: 0-1
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* @return The result of the read
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*/
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static inline uint64_t cvmx_llm_read_wide(cvmx_llm_address_t address, int set)
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{
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uint64_t value;
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if (set)
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{
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CVMX_MT_LLM_READ64_ADDR(1, address);
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CVMX_MF_LLM_DATA(1, value);
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}
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else
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{
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CVMX_MT_LLM_READ64_ADDR(0, address);
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CVMX_MF_LLM_DATA(0, value);
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}
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return value;
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}
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#define RLD_INIT_DELAY (1<<18)
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/* This structure describes the RLDRAM configuration for a board. This structure
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** must be populated with the correct values and passed to the initialization function.
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*/
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typedef struct
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{
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uint32_t cpu_hz; /* CPU frequency in Hz */
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char addr_rld0_fb_str [100]; /* String describing RLDRAM connections on rld 0 front (0) bunk*/
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char addr_rld0_bb_str [100]; /* String describing RLDRAM connections on rld 0 back (1) bunk*/
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char addr_rld1_fb_str [100]; /* String describing RLDRAM connections on rld 1 front (0) bunk*/
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char addr_rld1_bb_str [100]; /* String describing RLDRAM connections on rld 1 back (1) bunk*/
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uint8_t rld0_bunks; /* Number of bunks on rld 0 (0 is disabled) */
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uint8_t rld1_bunks; /* Number of bunks on rld 1 (0 is disabled) */
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uint16_t rld0_mbytes; /* mbytes on rld 0 */
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uint16_t rld1_mbytes; /* mbytes on rld 1 */
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uint16_t max_rld_clock_mhz; /* Maximum RLD clock in MHz, only used for CN58XX */
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} llm_descriptor_t;
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/**
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* Initialize LLM memory controller. This must be done
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* before the low latency memory can be used.
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* This is simply a wrapper around cvmx_llm_initialize_desc(),
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* and is deprecated.
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*
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* @return -1 on error
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* 0 on success
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*/
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int cvmx_llm_initialize(void);
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/**
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* Initialize LLM memory controller. This must be done
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* before the low latency memory can be used.
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*
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* @param llm_desc_ptr
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* Pointer to descriptor structure. If NULL
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* is passed, a default setting is used if available.
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*
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* @return -1 on error
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* Size of llm in bytes on success
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*/
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int cvmx_llm_initialize_desc(llm_descriptor_t *llm_desc_ptr);
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/**
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* Gets the default llm descriptor for the board code is being run on.
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*
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* @param llm_desc_ptr
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* Pointer to descriptor structure to be filled in. Contents are only
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* valid after successful completion. Must not be NULL.
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*
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* @return -1 on error
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* 0 on success
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*/
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int cvmx_llm_get_default_descriptor(llm_descriptor_t *llm_desc_ptr);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CVM_LLM_H__ */
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