c558b53ec8
twice, as advised in the atmel docs. Submitted by: Ian Lapore
365 lines
9.8 KiB
C
365 lines
9.8 KiB
C
/*-
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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* Copyright (c) 2012 Ian Lepore. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Driver for the at91 on-chip realtime clock.
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*
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* This driver does not currently support alarms, just date and time.
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*
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* The RTC on the AT91RM9200 resets when the core rests, so it is useless as a
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* source of time (except when the CPU clock is powered down to save power,
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* which we don't currently do). On AT91SAM9 chips, the RTC survives chip
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* reset, and there's provisions for it to keep time via battery backup if the
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* system loses power. On those systems, we use it as a RTC. We tell the two
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* apart because the century field is 19 on AT91RM9200 on reset, or on AT91SAM9
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* chips that haven't had their time properly set.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/clock.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <arm/at91/at91_rtcreg.h>
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#include "clock_if.h"
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/*
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* The driver has all the infrastructure to use interrupts but doesn't actually
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* have any need to do so right now. There's a non-zero cost for installing the
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* handler because the RTC shares the system interrupt (IRQ 1), and thus will
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* get called a lot for no reason at all.
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*/
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#define AT91_RTC_USE_INTERRUPTS_NOT
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struct at91_rtc_softc
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{
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device_t dev; /* Myself */
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void *intrhand; /* Interrupt handle */
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struct resource *irq_res; /* IRQ resource */
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struct resource *mem_res; /* Memory resource */
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struct mtx sc_mtx; /* basically a perimeter lock */
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};
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static inline uint32_t
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RD4(struct at91_rtc_softc *sc, bus_size_t off)
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{
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return bus_read_4(sc->mem_res, off);
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}
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static inline void
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WR4(struct at91_rtc_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_write_4(sc->mem_res, off, val);
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}
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#define AT91_RTC_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
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#define AT91_RTC_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
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#define AT91_RTC_LOCK_INIT(_sc) \
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mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
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"rtc", MTX_SPIN)
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#define AT91_RTC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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#define AT91_RTC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
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#define AT91_RTC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
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static devclass_t at91_rtc_devclass;
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/* bus entry points */
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static int at91_rtc_probe(device_t dev);
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static int at91_rtc_attach(device_t dev);
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static int at91_rtc_detach(device_t dev);
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/* helper routines */
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static int at91_rtc_activate(device_t dev);
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static void at91_rtc_deactivate(device_t dev);
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#ifdef AT91_RTC_USE_INTERRUPTS
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static int
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at91_rtc_intr(void *xsc)
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{
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struct at91_rtc_softc *sc;
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uint32_t status;
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sc = xsc;
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/* Must clear the status bits after reading them to re-arm. */
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status = RD4(sc, RTC_SR);
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WR4(sc, RTC_SCCR, status);
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if (status == 0)
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return;
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AT91_RTC_LOCK(sc);
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/* Do something here */
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AT91_RTC_UNLOCK(sc);
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wakeup(sc);
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return (FILTER_HANDLED);
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}
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#endif
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static int
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at91_rtc_probe(device_t dev)
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{
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device_set_desc(dev, "RTC");
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return (0);
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}
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static int
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at91_rtc_attach(device_t dev)
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{
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struct at91_rtc_softc *sc = device_get_softc(dev);
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int err;
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sc->dev = dev;
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err = at91_rtc_activate(dev);
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if (err)
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goto out;
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AT91_RTC_LOCK_INIT(sc);
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/*
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* Disable all interrupts in the hardware.
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* Clear all bits in the status register.
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* Set 24-hour-clock mode.
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*/
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WR4(sc, RTC_IDR, 0xffffffff);
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WR4(sc, RTC_SCCR, 0x1f);
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WR4(sc, RTC_MR, 0);
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#ifdef AT91_RTC_USE_INTERRUPTS
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err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC,
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at91_rtc_intr, NULL, sc, &sc->intrhand);
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if (err) {
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AT91_RTC_LOCK_DESTROY(sc);
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goto out;
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}
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#endif
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/*
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* Read the calendar register. If the century is 19 then the clock has
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* never been set. Try to store an invalid value into the register,
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* which will turn on the error bit in RTC_VER, and our getclock code
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* knows to return EINVAL if any error bits are on.
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*/
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if (RTC_CALR_CEN(RD4(sc, RTC_CALR)) == 19)
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WR4(sc, RTC_CALR, 0);
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/*
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* Register as a time of day clock with 1-second resolution.
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*/
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clock_register(dev, 1000000);
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out:
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if (err)
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at91_rtc_deactivate(dev);
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return (err);
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}
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/*
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* Cannot support detach, since there's no clock_unregister function.
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*/
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static int
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at91_rtc_detach(device_t dev)
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{
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return (EBUSY);
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}
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static int
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at91_rtc_activate(device_t dev)
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{
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struct at91_rtc_softc *sc;
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int rid;
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sc = device_get_softc(dev);
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL)
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goto errout;
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#ifdef AT91_RTC_USE_INTERRUPTS
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rid = 0;
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sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE | RF_SHAREABLE);
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if (sc->irq_res == NULL)
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goto errout;
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#endif
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return (0);
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errout:
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at91_rtc_deactivate(dev);
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return (ENOMEM);
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}
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static void
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at91_rtc_deactivate(device_t dev)
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{
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struct at91_rtc_softc *sc;
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sc = device_get_softc(dev);
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#ifdef AT91_RTC_USE_INTERRUPTS
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WR4(sc, RTC_IDR, 0xffffffff);
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if (sc->intrhand)
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bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
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sc->intrhand = 0;
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#endif
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bus_generic_detach(sc->dev);
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if (sc->mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY,
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rman_get_rid(sc->mem_res), sc->mem_res);
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sc->mem_res = 0;
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#ifdef AT91_RTC_USE_INTERRUPTS
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if (sc->irq_res)
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bus_release_resource(dev, SYS_RES_IRQ,
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rman_get_rid(sc->irq_res), sc->irq_res);
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sc->irq_res = 0;
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#endif
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return;
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}
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/*
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* Get the time of day clock and return it in ts.
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* Return 0 on success, an error number otherwise.
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*/
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static int
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at91_rtc_gettime(device_t dev, struct timespec *ts)
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{
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struct clocktime ct;
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uint32_t calr, calr2, timr, timr2;
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struct at91_rtc_softc *sc;
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sc = device_get_softc(dev);
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/* If the error bits are set we can't return useful values. */
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if (RD4(sc, RTC_VER) & (RTC_VER_NVTIM | RTC_VER_NVCAL))
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return EINVAL;
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/*
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* The RTC hardware can update registers while the CPU is reading them.
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* The manual advises reading until you obtain the same values twice.
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* Interleaving the reads (rather than timr, timr2, calr, calr2 order)
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* also ensures we don't miss a midnight rollover/carry between reads.
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*/
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do {
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timr = RD4(sc, RTC_TIMR);
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calr = RD4(sc, RTC_CALR);
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timr2 = RD4(sc, RTC_TIMR);
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calr2 = RD4(sc, RTC_CALR);
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} while (timr != timr2 || calr != calr2);
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ct.nsec = 0;
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ct.sec = RTC_TIMR_SEC(timr);
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ct.min = RTC_TIMR_MIN(timr);
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ct.hour = RTC_TIMR_HR(timr);
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ct.year = RTC_CALR_CEN(calr) * 100 + RTC_CALR_YEAR(calr);
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ct.mon = RTC_CALR_MON(calr);
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ct.day = RTC_CALR_DAY(calr);
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ct.dow = -1;
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return clock_ct_to_ts(&ct, ts);
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}
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/*
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* Set the time of day clock based on the value of the struct timespec arg.
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* Return 0 on success, an error number otherwise.
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*/
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static int
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at91_rtc_settime(device_t dev, struct timespec *ts)
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{
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struct at91_rtc_softc *sc;
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struct clocktime ct;
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int rv;
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sc = device_get_softc(dev);
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clock_ts_to_ct(ts, &ct);
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/*
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* Can't set the clock unless a second has elapsed since we last did so.
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*/
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while ((RD4(sc, RTC_SR) & RTC_SR_SECEV) == 0)
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cpu_spinwait();
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/*
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* Stop the clocks for an update; wait until hardware is ready.
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* Clear the update-ready status after it gets asserted (the manual says
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* to do this before updating the value registers).
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*/
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WR4(sc, RTC_CR, RTC_CR_UPDCAL | RTC_CR_UPDTIM);
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while ((RD4(sc, RTC_SR) & RTC_SR_ACKUPD) == 0)
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cpu_spinwait();
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WR4(sc, RTC_SCCR, RTC_SR_ACKUPD);
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/*
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* Set the values in the hardware, then check whether the hardware was
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* happy with them so we can return the correct status.
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*/
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WR4(sc, RTC_TIMR, RTC_TIMR_MK(ct.hour, ct.min, ct.sec));
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WR4(sc, RTC_CALR, RTC_CALR_MK(ct.year, ct.mon, ct.day, ct.dow+1));
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if (RD4(sc, RTC_VER) & (RTC_VER_NVTIM | RTC_VER_NVCAL))
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rv = EINVAL;
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else
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rv = 0;
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/*
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* Restart the clocks (turn off the update bits).
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* Clear the second-event bit (because the manual says to).
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*/
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WR4(sc, RTC_CR, RD4(sc, RTC_CR) & ~(RTC_CR_UPDCAL | RTC_CR_UPDTIM));
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WR4(sc, RTC_SCCR, RTC_SR_SECEV);
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return (0);
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}
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static device_method_t at91_rtc_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, at91_rtc_probe),
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DEVMETHOD(device_attach, at91_rtc_attach),
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DEVMETHOD(device_detach, at91_rtc_detach),
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/* clock interface */
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DEVMETHOD(clock_gettime, at91_rtc_gettime),
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DEVMETHOD(clock_settime, at91_rtc_settime),
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DEVMETHOD_END
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};
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static driver_t at91_rtc_driver = {
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"at91_rtc",
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at91_rtc_methods,
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sizeof(struct at91_rtc_softc),
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};
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DRIVER_MODULE(at91_rtc, atmelarm, at91_rtc_driver, at91_rtc_devclass, 0, 0);
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