Justin T. Gibbs 499c4ce9f6 Clear the DFCNTRL register after every busfree. ... When setting the HCNT registers, do so in ascending order. When performing tagged queueing in non-paging mode, also check the disconnected bit in the SCB as extra sanity during a reconection. Make the labels in the DMA routine more sane. When doing a DMA, if we see the DMADONE condition come true, we can simply turn of the DMA enable bits in DFCNTRL without testing the FIFO state as HDONE is true when DMADONE is true and this emplies the FIFO is empty. These changes clear up the data overrun error messages and seem to prevent the "timed out in data-in phase" problems.		1997-02-11 17:07:54 +00:00
..
aicasm	Make the long-awaited change from $Id$ to $FreeBSD$	1997-01-14 07:20:47 +00:00
aic7xxx_asm.1	John Aycock's BSD copyrighted sequencer assembler and sequencer code. This	1995-04-15 21:45:56 +00:00
aic7xxx_asm.c	Make the long-awaited change from $Id$ to $FreeBSD$	1997-01-14 07:20:47 +00:00
aic7xxx_reg.h	Clear the channel after (re)selection instead of once we see the bus go	1997-02-09 03:23:28 +00:00
aic7xxx.seq	Clear the DFCNTRL register after every busfree.	1997-02-11 17:07:54 +00:00
aicasm.c	Make the long-awaited change from $Id$ to $FreeBSD$	1997-01-14 07:20:47 +00:00