0d356a5349
OPAL unconditionally enters secondary CPUs with only HV and SF set. I tried writing a secondary entry point instead, but OPAL rejected it and I am unsure why, so I resorted to making the system reset interrupt endian-flexible. This means we take a slight performance hit on wakeup on LE, but it is a good stopgap until we can figure out a reliable way to make OPAL enter where we want it to. It probably makes sense to have it around anyway, because I can imagine scenarios where the cpu resets itself to BE and does a software reset. Sponsored by: Tag1 Consulting, Inc.
261 lines
7.5 KiB
C
261 lines
7.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-4-Clause
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*
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $NetBSD: asm.h,v 1.6.18.1 2000/07/25 08:37:14 kleink Exp $
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ASM_H_
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#define _MACHINE_ASM_H_
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#include <sys/cdefs.h>
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#if defined(PIC) && !defined(__powerpc64__)
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#define PIC_PROLOGUE XXX
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#define PIC_EPILOGUE XXX
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#define PIC_PLT(x) x@plt
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#ifdef __STDC__
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#define PIC_GOT(x) XXX
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#else /* not __STDC__ */
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#define PIC_GOT(x) XXX
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#endif /* __STDC__ */
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#else
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#define PIC_PROLOGUE
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#define PIC_EPILOGUE
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#define PIC_PLT(x) x
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#define PIC_GOT(x) x
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#endif
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#define CNAME(csym) csym
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#define ASMNAME(asmsym) asmsym
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#ifdef __powerpc64__
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#define HIDENAME(asmsym) __CONCAT(_,asmsym)
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#else
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#define HIDENAME(asmsym) __CONCAT(.,asmsym)
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#endif
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#if !defined(_CALL_ELF) || _CALL_ELF == 1
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#ifdef _KERNEL
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/* ELFv1 kernel uses global dot symbols */
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#define DOT_LABEL(name) __CONCAT(.,name)
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#define TYPE_ENTRY(name) .size name,24; \
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.type DOT_LABEL(name),@function; \
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.globl DOT_LABEL(name);
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#define END_SIZE(name) .size DOT_LABEL(name),.-DOT_LABEL(name);
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#else /* !_KERNEL */
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/* ELFv1 user code uses local function entry points */
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#define DOT_LABEL(name) __CONCAT(.L.,name)
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#define TYPE_ENTRY(name) .type name,@function;
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#define END_SIZE(name) .size name,.-DOT_LABEL(name);
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#endif /* _KERNEL */
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#else
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/* ELFv2 doesn't have any of this complication */
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#define DOT_LABEL(name) name
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#define TYPE_ENTRY(name) .type name,@function;
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#define END_SIZE(name) .size name,.-DOT_LABEL(name);
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#endif
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#define _GLOBAL(name) \
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.data; \
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.p2align 2; \
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.globl name; \
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name:
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#ifdef __powerpc64__
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#define TOC_NAME_FOR_REF(name) __CONCAT(.L,name)
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#define TOC_REF(name) TOC_NAME_FOR_REF(name)@toc
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#define TOC_ENTRY(name) \
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.section ".toc","aw"; \
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TOC_NAME_FOR_REF(name): \
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.tc name[TC],name
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#endif
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#ifdef __powerpc64__
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#if !defined(_CALL_ELF) || _CALL_ELF == 1
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#define _ENTRY(name) \
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.section ".text"; \
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.p2align 2; \
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.globl name; \
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.section ".opd","aw"; \
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.p2align 3; \
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name: \
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.quad DOT_LABEL(name),.TOC.@tocbase,0; \
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.previous; \
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.p2align 4; \
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TYPE_ENTRY(name) \
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DOT_LABEL(name):
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#define _NAKED_ENTRY(name) _ENTRY(name)
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#else
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#define _ENTRY(name) \
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.text; \
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.p2align 4; \
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.globl name; \
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.type name,@function; \
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name: \
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addis %r2, %r12, (.TOC.-name)@ha; \
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addi %r2, %r2, (.TOC.-name)@l; \
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.localentry name, .-name;
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/* "Naked" function entry. No TOC prologue for ELFv2. */
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#define _NAKED_ENTRY(name) \
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.text; \
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.p2align 4; \
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.globl name; \
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.type name,@function; \
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name: \
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.localentry name, .-name;
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#endif
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#define _END(name) \
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.long 0; \
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.byte 0,0,0,0,0,0,0,0; \
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END_SIZE(name)
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#define LOAD_ADDR(reg, var) \
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lis reg, var@highest; \
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ori reg, reg, var@higher; \
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rldicr reg, reg, 32, 31; \
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oris reg, reg, var@h; \
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ori reg, reg, var@l;
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#else /* !__powerpc64__ */
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#define _ENTRY(name) \
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.text; \
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.p2align 4; \
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.globl name; \
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.type name,@function; \
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name:
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#define _END(name)
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#define _NAKED_ENTRY(name) _ENTRY(name)
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#define LOAD_ADDR(reg, var) \
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lis reg, var@ha; \
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ori reg, reg, var@l;
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#endif /* __powerpc64__ */
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#if defined(PROF) || (defined(_KERNEL) && defined(GPROF))
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# ifdef __powerpc64__
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# define _PROF_PROLOGUE mflr 0; \
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std 3,48(1); \
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std 4,56(1); \
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std 5,64(1); \
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std 0,16(1); \
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stdu 1,-112(1); \
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bl _mcount; \
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nop; \
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ld 0,112+16(1); \
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ld 3,112+48(1); \
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ld 4,112+56(1); \
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ld 5,112+64(1); \
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mtlr 0; \
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addi 1,1,112
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# else
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# define _PROF_PROLOGUE mflr 0; stw 0,4(1); bl _mcount
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# endif
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#else
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# define _PROF_PROLOGUE
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#endif
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#define ASENTRY(y) _ENTRY(ASMNAME(y)); _PROF_PROLOGUE
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#define END(y) _END(CNAME(y))
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#define ENTRY(y) _ENTRY(CNAME(y)); _PROF_PROLOGUE
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#define GLOBAL(y) _GLOBAL(CNAME(y))
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#define ASENTRY_NOPROF(y) _ENTRY(ASMNAME(y))
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#define ENTRY_NOPROF(y) _ENTRY(CNAME(y))
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/* Load NIA without affecting branch prediction */
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#define LOAD_LR_NIA bcl 20, 31, .+4
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/*
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* Magic sequence to return to native endian.
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* Overwrites r0 and r11.
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*
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* The encoding of the instruction "tdi 0, %r0, 0x48" in opposite endian
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* happens to be "b . + 8". This is useful because we can write a sequence
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* of instructions that can execute in either endian.
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*
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* Use a sequence of handcoded instructions that switches contexts to the
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* instruction following the sequence, but with the correct PSL_LE bit.
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*
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* The same sequence works for both BE and LE because the xori will flip
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* the bit to the other state, and the code only runs when running in the
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* wrong endian.
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*
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* This sequence is NMI-reentrant.
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*
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* Do not change the length of this sequence without looking at the users,
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* this is used in size-constrained places like the reset vector!
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*/
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#define RETURN_TO_NATIVE_ENDIAN \
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tdi 0, %r0, 0x48; /* Endian swapped: b . + 8 */\
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b 1f; /* Will fall through to here if correct */\
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.long 0xa600607d; /* mfmsr %r11 */\
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.long 0x00000038; /* li %r0, 0 */\
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.long 0x6401617d; /* mtmsrd %r0, 1 (L=1 EE,RI bits only) */\
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.long 0x01006b69; /* xori %r11, %r11, 0x1 (PSL_LE) */\
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.long 0xa602087c; /* mflr %r0 */\
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.long 0x05009f42; /* LOAD_LR_NIA */\
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.long 0xa6037b7d; /* 0: mtsrr1 %r11 */\
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.long 0xa602687d; /* mflr %r11 */\
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.long 0x18006b39; /* addi %r11, %r11, (1f - 0b) */\
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.long 0xa6037a7d; /* mtsrr0 %r11 */\
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.long 0xa603087c; /* mtlr %r0 */\
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.long 0x2400004c; /* rfid */\
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1: /* RETURN_TO_NATIVE_ENDIAN */
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#define ASMSTR .asciz
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#define RCSID(x) .text; .asciz x
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#undef __FBSDID
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#if !defined(lint) && !defined(STRIP_FBSDID)
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#define __FBSDID(s) .ident s
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#else
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#define __FBSDID(s) /* nothing */
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#endif /* not lint and not STRIP_FBSDID */
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#define WEAK_REFERENCE(sym, alias) \
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.weak alias; \
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.equ alias,sym
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#ifdef __STDC__
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#define WARN_REFERENCES(_sym,_msg) \
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.section .gnu.warning. ## _sym ; .ascii _msg ; .text
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#else
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#define WARN_REFERENCES(_sym,_msg) \
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.section .gnu.warning./**/_sym ; .ascii _msg ; .text
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#endif /* __STDC__ */
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#endif /* !_MACHINE_ASM_H_ */
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