129 lines
3.9 KiB
C
129 lines
3.9 KiB
C
/*-
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* Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <machine/fdt.h>
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#include <machine/smp.h>
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#include <machine/platformvar.h>
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#include <machine/pmap.h>
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#include <arm/nvidia/tegra124/tegra124_mp.h>
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#define PMC_PHYSBASE 0x7000e400
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#define PMC_SIZE 0x400
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#define PMC_CONTROL_REG 0x0
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#define PMC_PWRGATE_TOGGLE 0x30
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#define PCM_PWRGATE_TOGGLE_START (1 << 8)
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#define PMC_PWRGATE_STATUS 0x38
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#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000 /* exception vectors */
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#define TEGRA_EXCEPTION_VECTORS_SIZE 1024
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#define TEGRA_EXCEPTION_VECTOR_ENTRY 0x100
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void
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tegra124_mp_setmaxid(platform_t plat)
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{
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int ncpu;
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/* If we've already set the global vars don't bother to do it again. */
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if (mp_ncpus != 0)
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return;
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/* Read current CP15 Cache Size ID Register */
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ncpu = cp15_l2ctlr_get();
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ncpu = CPUV7_L2CTLR_NPROC(ncpu);
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mp_ncpus = ncpu;
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mp_maxid = ncpu - 1;
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}
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void
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tegra124_mp_start_ap(platform_t plat)
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{
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bus_space_handle_t pmc;
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bus_space_handle_t exvec;
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int i;
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uint32_t val;
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uint32_t mask;
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if (bus_space_map(fdtbus_bs_tag, PMC_PHYSBASE, PMC_SIZE, 0, &pmc) != 0)
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panic("Couldn't map the PMC\n");
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if (bus_space_map(fdtbus_bs_tag, TEGRA_EXCEPTION_VECTORS_BASE,
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TEGRA_EXCEPTION_VECTORS_SIZE, 0, &exvec) != 0)
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panic("Couldn't map the exception vectors\n");
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bus_space_write_4(fdtbus_bs_tag, exvec , TEGRA_EXCEPTION_VECTOR_ENTRY,
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pmap_kextract((vm_offset_t)mpentry));
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bus_space_read_4(fdtbus_bs_tag, exvec , TEGRA_EXCEPTION_VECTOR_ENTRY);
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/* Wait until POWERGATE is ready (max 20 APB cycles). */
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do {
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val = bus_space_read_4(fdtbus_bs_tag, pmc,
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PMC_PWRGATE_TOGGLE);
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} while ((val & PCM_PWRGATE_TOGGLE_START) != 0);
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for (i = 1; i < mp_ncpus; i++) {
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val = bus_space_read_4(fdtbus_bs_tag, pmc, PMC_PWRGATE_STATUS);
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mask = 1 << (i + 8); /* cpu mask */
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if ((val & mask) == 0) {
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/* Wait until POWERGATE is ready (max 20 APB cycles). */
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do {
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val = bus_space_read_4(fdtbus_bs_tag, pmc,
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PMC_PWRGATE_TOGGLE);
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} while ((val & PCM_PWRGATE_TOGGLE_START) != 0);
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bus_space_write_4(fdtbus_bs_tag, pmc,
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PMC_PWRGATE_TOGGLE,
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PCM_PWRGATE_TOGGLE_START | (8 + i));
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/* Wait until CPU is powered */
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do {
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val = bus_space_read_4(fdtbus_bs_tag, pmc,
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PMC_PWRGATE_STATUS);
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} while ((val & mask) == 0);
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}
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}
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dsb();
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sev();
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bus_space_unmap(fdtbus_bs_tag, pmc, PMC_SIZE);
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bus_space_unmap(fdtbus_bs_tag, exvec, TEGRA_EXCEPTION_VECTORS_SIZE);
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}
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