Marcel Moolenaar 4827e0cd5c Make sure bus space accesses use unorder memory loads and stores. ... Memory accesses are posted in program order by virtue of the uncacheable memory attribute. Since GCC, by default, adds acquire and release semantics to volatile memory loads and stores, we need to use inline assembly to guarantee it. With inline assembly, we don't need volatile pointers anymore. Itanium does not support semaphore instructions to uncacheable memory.		2009-12-03 04:06:48 +00:00
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acpica	Import ACPICA 20090521.	2009-06-05 18:44:36 +00:00
compile
conf	Add PRINTF_BUFR_SIZE=128, since we have SMP by default.	2009-10-24 20:35:34 +00:00
disasm	Fix disassembly of the invala, itc, itr and hint instructions	2007-10-16 02:49:40 +00:00
ia32	Add trivial implementation for the freebsd32_sysarch on ia64.	2009-04-01 19:23:07 +00:00
ia64	Make sure bus space accesses use unorder memory loads and stores.	2009-12-03 04:06:48 +00:00
include	Make sure bus space accesses use unorder memory loads and stores.	2009-12-03 04:06:48 +00:00
isa	Remove isa_irq_pending(). It's not used.	2009-04-24 03:43:20 +00:00
pci