7c6b05d280
- Huge old hdac driver was split into three independent pieces: HDA controller driver (hdac), HDA CODEC driver (hdacc) and HDA sudio function driver (hdaa). - Support for multichannel recording was added. Now, as specification defines, driver checks input associations for pins with sequence numbers 14 and 15, and if found (usually) -- works as before, mixing signals together. If it doesn't, it configures input association as multichannel. - Signal tracer was improved to look for cases where several DACs/ADCs in CODEC can work with the same audio signal. If such case found, driver registers additional playback/record stream (channel) for the pcm device. - New controller streams reservation mechanism was implemented. That allows to have more pcm devices then streams supported by the controller (usually 4 in each direction). Now it limits only number of simultaneously transferred audio streams, that is rarely reachable and properly reported if happens. - Codec pins and GPIO signals configuration was exported via set of writable sysctls. Another sysctl dev.hdaa.X.reconfig allows to trigger driver reconfiguration in run-time. - Driver now decodes pins location and connector type names. In some cases it allows to hint user where on the system case connectors, related to the pcm device, are located. Number of channels supported by pcm device, reported now (if it is not 2), should also make search easier. - Added workaround for digital mic on some Asus laptops/netbooks. MFC after: 2 months Sponsored by: iXsystems, Inc.
223 lines
7.6 KiB
C
223 lines
7.6 KiB
C
/*-
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* Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
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* Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _HDAC_PRIVATE_H_
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#define _HDAC_PRIVATE_H_
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/****************************************************************************
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* Miscellaneous defines
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****************************************************************************/
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#define HDAC_CODEC_MAX 16
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/****************************************************************************
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* Helper Macros
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****************************************************************************/
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#define HDAC_READ_1(mem, offset) \
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bus_space_read_1((mem)->mem_tag, (mem)->mem_handle, (offset))
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#define HDAC_READ_2(mem, offset) \
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bus_space_read_2((mem)->mem_tag, (mem)->mem_handle, (offset))
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#define HDAC_READ_4(mem, offset) \
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bus_space_read_4((mem)->mem_tag, (mem)->mem_handle, (offset))
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#define HDAC_WRITE_1(mem, offset, value) \
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bus_space_write_1((mem)->mem_tag, (mem)->mem_handle, (offset), (value))
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#define HDAC_WRITE_2(mem, offset, value) \
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bus_space_write_2((mem)->mem_tag, (mem)->mem_handle, (offset), (value))
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#define HDAC_WRITE_4(mem, offset, value) \
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bus_space_write_4((mem)->mem_tag, (mem)->mem_handle, (offset), (value))
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#define HDAC_ISDCTL(sc, n) (_HDAC_ISDCTL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDSTS(sc, n) (_HDAC_ISDSTS((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDPICB(sc, n) (_HDAC_ISDPICB((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDCBL(sc, n) (_HDAC_ISDCBL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDLVI(sc, n) (_HDAC_ISDLVI((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDFIFOD(sc, n) (_HDAC_ISDFIFOD((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDFMT(sc, n) (_HDAC_ISDFMT((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDBDPL(sc, n) (_HDAC_ISDBDPL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDBDPU(sc, n) (_HDAC_ISDBDPU((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDCTL(sc, n) (_HDAC_OSDCTL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDSTS(sc, n) (_HDAC_OSDSTS((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDPICB(sc, n) (_HDAC_OSDPICB((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDCBL(sc, n) (_HDAC_OSDCBL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDLVI(sc, n) (_HDAC_OSDLVI((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDFIFOD(sc, n) (_HDAC_OSDFIFOD((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDBDPL(sc, n) (_HDAC_OSDBDPL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDBDPU(sc, n) (_HDAC_OSDBDPU((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDCTL(sc, n) (_HDAC_BSDCTL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDSTS(sc, n) (_HDAC_BSDSTS((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDPICB(sc, n) (_HDAC_BSDPICB((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDCBL(sc, n) (_HDAC_BSDCBL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDLVI(sc, n) (_HDAC_BSDLVI((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDFIFOD(sc, n) (_HDAC_BSDFIFOD((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDBDPL(sc, n) (_HDAC_BSDBDPL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDBDPU(sc, n) (_HDAC_BSDBDPU((n), (sc)->num_iss, (sc)->num_oss))
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/****************************************************************************
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* Custom hdac malloc type
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****************************************************************************/
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MALLOC_DECLARE(M_HDAC);
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/****************************************************************************
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* struct hdac_mem
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*
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* Holds the resources necessary to describe the physical memory associated
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* with the device.
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****************************************************************************/
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struct hdac_mem {
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struct resource *mem_res;
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int mem_rid;
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bus_space_tag_t mem_tag;
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bus_space_handle_t mem_handle;
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};
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/****************************************************************************
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* struct hdac_irq
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*
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* Holds the resources necessary to describe the irq associated with the
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* device.
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****************************************************************************/
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struct hdac_irq {
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struct resource *irq_res;
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int irq_rid;
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void *irq_handle;
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};
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/****************************************************************************
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* struct hdac_dma
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*
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* This structure is used to hold all the information to manage the dma
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* states.
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****************************************************************************/
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struct hdac_dma {
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bus_dma_tag_t dma_tag;
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bus_dmamap_t dma_map;
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bus_addr_t dma_paddr;
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bus_size_t dma_size;
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caddr_t dma_vaddr;
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};
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/****************************************************************************
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* struct hdac_rirb
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*
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* Hold a response from a verb sent to a codec received via the rirb.
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****************************************************************************/
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struct hdac_rirb {
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uint32_t response;
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uint32_t response_ex;
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};
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#define HDAC_RIRB_RESPONSE_EX_SDATA_IN_MASK 0x0000000f
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#define HDAC_RIRB_RESPONSE_EX_SDATA_IN_OFFSET 0
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#define HDAC_RIRB_RESPONSE_EX_UNSOLICITED 0x00000010
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#define HDAC_RIRB_RESPONSE_EX_SDATA_IN(response_ex) \
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(((response_ex) & HDAC_RIRB_RESPONSE_EX_SDATA_IN_MASK) >> \
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HDAC_RIRB_RESPONSE_EX_SDATA_IN_OFFSET)
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struct hdac_bdle {
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volatile uint32_t addrl;
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volatile uint32_t addrh;
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volatile uint32_t len;
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volatile uint32_t ioc;
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} __packed;
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struct hdac_stream {
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device_t dev;
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struct hdac_dma bdl;
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int dir;
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int stream;
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int blksz;
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int running;
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uint16_t format;
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};
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struct hdac_softc {
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device_t dev;
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struct mtx *lock;
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struct intr_config_hook intrhook;
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struct hdac_mem mem;
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struct hdac_irq irq;
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uint32_t quirks_on;
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uint32_t quirks_off;
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uint32_t flags;
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#define HDAC_F_DMA_NOCACHE 0x00000001
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int num_iss;
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int num_oss;
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int num_bss;
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int num_ss;
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int num_sdo;
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int support_64bit;
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int corb_size;
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struct hdac_dma corb_dma;
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int corb_wp;
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int rirb_size;
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struct hdac_dma rirb_dma;
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int rirb_rp;
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struct hdac_dma pos_dma;
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bus_dma_tag_t chan_dmat;
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/* Polling */
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int polling;
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int poll_ival;
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struct callout poll_callout;
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int unsol_registered;
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struct task unsolq_task;
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#define HDAC_UNSOLQ_MAX 64
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#define HDAC_UNSOLQ_READY 0
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#define HDAC_UNSOLQ_BUSY 1
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int unsolq_rp;
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int unsolq_wp;
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int unsolq_st;
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uint32_t unsolq[HDAC_UNSOLQ_MAX];
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struct hdac_stream *streams;
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struct {
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device_t dev;
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uint16_t vendor_id;
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uint16_t device_id;
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uint8_t revision_id;
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uint8_t stepping_id;
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int pending;
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uint32_t response;
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} codecs[HDAC_CODEC_MAX];
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};
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#endif
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