53b8229e97
into and out of the halt state very quickly. Submitted by: Andriy Gapon <avg at icyb dot net dot ua> MFC after: 1 week
141 lines
4.1 KiB
C
141 lines
4.1 KiB
C
/*-
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* Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
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* Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2000 BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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/*
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* Chipset fixups.
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*
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* These routines are invoked during the probe phase for devices which
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* typically don't have specific device drivers, but which require
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* some cleaning up.
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*/
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static int fixup_pci_probe(device_t dev);
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static void fixwsc_natoma(device_t dev);
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static void fixc1_nforce2(device_t dev);
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static device_method_t fixup_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, fixup_pci_probe),
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DEVMETHOD(device_attach, bus_generic_attach),
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{ 0, 0 }
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};
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static driver_t fixup_pci_driver = {
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"fixup_pci",
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fixup_pci_methods,
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0,
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};
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static devclass_t fixup_pci_devclass;
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DRIVER_MODULE(fixup_pci, pci, fixup_pci_driver, fixup_pci_devclass, 0, 0);
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static int
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fixup_pci_probe(device_t dev)
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{
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switch (pci_get_devid(dev)) {
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case 0x12378086: /* Intel 82440FX (Natoma) */
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fixwsc_natoma(dev);
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break;
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case 0x01e010de: /* nVidia nForce2 */
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fixc1_nforce2(dev);
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break;
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}
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return(ENXIO);
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}
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static void
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fixwsc_natoma(device_t dev)
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{
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int pmccfg;
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pmccfg = pci_read_config(dev, 0x50, 2);
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#if defined(SMP)
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if (pmccfg & 0x8000) {
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printf("Correcting Natoma config for SMP\n");
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pmccfg &= ~0x8000;
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pci_write_config(dev, 0x50, pmccfg, 2);
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}
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#else
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if ((pmccfg & 0x8000) == 0) {
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printf("Correcting Natoma config for non-SMP\n");
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pmccfg |= 0x8000;
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pci_write_config(dev, 0x50, pmccfg, 2);
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}
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#endif
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}
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/*
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* Set the SYSTEM_IDLE_TIMEOUT to 80 ns on nForce2 systems to work
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* around a hang that is triggered when the CPU generates a very fast
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* CONNECT/HALT cycle sequence. Specifically, the hang can result in
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* the lapic timer being stopped.
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*
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* This requires changing the value for config register at offset 0x6c
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* for the Host-PCI bridge at bus/dev/function 0/0/0:
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*
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* Chip Current Value New Value
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* ---- ---------- ----------
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* C17 0x1F0FFF01 0x1F01FF01
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* C18D 0x9F0FFF01 0x9F01FF01
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*
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* We do this by always clearing the bits in 0x000e0000.
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*
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* See also: http://lkml.org/lkml/2004/5/3/157
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*/
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static void
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fixc1_nforce2(device_t dev)
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{
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uint32_t val;
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if (pci_get_bus(dev) == 0 && pci_get_slot(dev) == 0 &&
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pci_get_function(dev) == 0) {
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val = pci_read_config(dev, 0x6c, 4);
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if (val & 0x000e0000) {
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printf("Correcting nForce2 C1 CPU disconnect hangs\n");
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val &= ~0x000e0000;
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pci_write_config(dev, 0x6c, val, 4);
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}
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}
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}
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