Andrew Turner a58fc7cb88 Disable the use of the quantum cache in the GICv3 ITS ... This uses UMA to allocate space. It causes issues when there are multiple ITS devices in the system where interrupts are not allocated from a low address on some interrupt controllers. Disabling the quantum cache fixes this on the Neoverse N1 SDP. MFC after: 2 weeks Sponsored by: DARPA, AFRL		2020-02-03 13:47:41 +00:00
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acpica	Ignore the SMMUv3 and PMCG interrupt controller in the IORT tables	2020-01-31 09:51:38 +00:00
arm64	Disable the use of the quantum cache in the GICv3 ITS	2020-02-03 13:47:41 +00:00
cavium	Rename the ThunderX CPU identification macros to include the X. This is the	2018-06-13 12:17:11 +00:00
cloudabi32	Use uintptr_t instead of register_t * for the stack base.	2019-12-03 23:17:54 +00:00
cloudabi64	Use uintptr_t instead of register_t * for the stack base.	2019-12-03 23:17:54 +00:00
conf	arm64: rockchip: Add RK3399 PWM driver	2020-01-16 21:25:13 +00:00
coresight	Extract eventfilter declarations to sys/_eventfilter.h	2019-05-20 00:38:23 +00:00
include	Print missing ID_AA64PFR{0,1}_EL1 register fields.	2020-01-23 16:10:38 +00:00
intel	Add support for Intel Stratix 10 platform.	2019-09-13 16:50:57 +00:00
linux	sysent targets: further cleanup and deduplication	2020-01-18 20:37:45 +00:00
qualcomm	Enable Qualcomm Debug Subsystem (QDSS) block on MSM8916 SoC.	2018-04-10 12:53:48 +00:00
rockchip	Enable USB3 support for Rockchip RK3328 SoC.	2020-01-29 09:36:59 +00:00