51 lines
2.3 KiB
C
51 lines
2.3 KiB
C
/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define RSTMGR_STAT 0x0 /* Status */
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#define RSTMGR_CTRL 0x4 /* Control */
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#define CTRL_SWWARMRSTREQ (1 << 1) /* Trigger warm reset */
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#define RSTMGR_COUNTS 0x8 /* Reset Cycles Count */
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#define RSTMGR_MPUMODRST 0x10 /* MPU Module Reset */
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#define MPUMODRST_CPU1 (1 << 1)
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#define RSTMGR_PERMODRST 0x14 /* Peripheral Module Reset */
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#define RSTMGR_PER2MODRST 0x18 /* Peripheral 2 Module Reset */
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#define RSTMGR_BRGMODRST 0x1C /* Bridge Module Reset */
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#define BRGMODRST_FPGA2HPS (1 << 2)
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#define BRGMODRST_LWHPS2FPGA (1 << 1)
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#define BRGMODRST_HPS2FPGA (1 << 0)
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#define RSTMGR_MISCMODRST 0x20 /* Miscellaneous Module Reset */
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#define RSTMGR_A10_CTRL 0xC /* Control */
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#define RSTMGR_A10_MPUMODRST 0x20 /* MPU Module Reset */
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int rstmgr_warmreset(uint32_t reg);
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