Konstantin Belousov 6b7c46afec Right now, for non-coherent DMARs, page table update code flushes the ... cache for whole page containing modified pte, and more, only last page in the series of the consequtive pages is flushed (i.e. the affected mappings should be larger than 2MB). Avoid excessive flushing and do missed neccessary flushing, by splitting invalidation and unmapping. For now, flush exactly the range of the changed pte. This is still somewhat bigger than neccessary, since pte is 8 bytes, while cache flush line is at least 32 bytes. The originator of the issue reports that after the change, 'dmar_bus_dmamap_unload went from 13,288 cycles down to 3,257. dmar_bus_dmamap_load_buffer went from 9,686 cycles down to 3,517. and I am now able to get line 1GbE speed with Netperf TCP (even with 1K message size).' Diagnosed and tested by: Nadav Amit <nadav.amit@gmail.com> Sponsored by: The FreeBSD Foundation MFC after: 1 week		2015-01-11 20:27:15 +00:00
..
busdma_dmar.c	Fix calculation of requester for PCI device behind PCIe/PCI bridge.	2015-01-10 23:12:49 +00:00
busdma_dmar.h
intel_ctx.c	Right now, for non-coherent DMARs, page table update code flushes the	2015-01-11 20:27:15 +00:00
intel_dmar.h	Right now, for non-coherent DMARs, page table update code flushes the	2015-01-11 20:27:15 +00:00
intel_drv.c	Remove ia64.	2014-07-07 00:27:09 +00:00
intel_fault.c	Print rid when announcing DMAR context creation. Print sid when fault	2015-01-10 22:57:08 +00:00
intel_gas.c	Add support for queued invalidation.	2013-11-01 17:38:52 +00:00
intel_idpgtbl.c	Right now, for non-coherent DMARs, page table update code flushes the	2015-01-11 20:27:15 +00:00
intel_qi.c	Add support for queued invalidation.	2013-11-01 17:38:52 +00:00
intel_quirks.c
intel_reg.h	Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this	2013-11-30 22:17:27 +00:00
intel_utils.c	Right now, for non-coherent DMARs, page table update code flushes the	2015-01-11 20:27:15 +00:00