ee41e38d42
Intel Stratix 10 SoC includes a quad-core arm64 cluster and FPGA fabric. This adds support for reconfiguring FPGA. Accessing FPGA core of this SoC require the level of privilege EL3, while kernel runs in EL1 (lower) level of privilege. This provides an Intel service layer interface that uses SMCCC to pass queries to the secure-monitor (EL3). Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D21454
272 lines
6.0 KiB
C
272 lines
6.0 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory (Department of Computer Science and
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* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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* DARPA SSITH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Intel Stratix 10 Service Layer
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/conf.h>
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#include <sys/uio.h>
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#include <sys/vmem.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm64/intel/intel-smc.h>
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#include <arm64/intel/stratix10-svc.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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struct s10_svc_softc {
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device_t dev;
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vmem_t *vmem;
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intel_smc_callfn_t callfn;
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};
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static int
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s10_data_claim(struct s10_svc_softc *sc)
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{
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struct arm_smccc_res res;
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register_t a0, a1, a2;
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int ret;
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ret = 0;
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while (1) {
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a0 = INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE;
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a1 = 0;
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a2 = 0;
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ret = sc->callfn(a0, a1, a2, 0, 0, 0, 0, 0, &res);
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if (ret == INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY)
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continue;
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break;
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}
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return (ret);
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}
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int
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s10_svc_send(device_t dev, struct s10_svc_msg *msg)
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{
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struct s10_svc_softc *sc;
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struct arm_smccc_res res;
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register_t a0, a1, a2;
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int ret;
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sc = device_get_softc(dev);
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a0 = 0;
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a1 = 0;
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a2 = 0;
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switch (msg->command) {
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case COMMAND_RECONFIG:
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a0 = INTEL_SIP_SMC_FPGA_CONFIG_START;
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a1 = msg->flags;
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break;
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case COMMAND_RECONFIG_DATA_SUBMIT:
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a0 = INTEL_SIP_SMC_FPGA_CONFIG_WRITE;
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a1 = (uint64_t)msg->payload;
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a2 = (uint64_t)msg->payload_length;
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break;
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case COMMAND_RECONFIG_DATA_CLAIM:
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ret = s10_data_claim(sc);
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return (ret);
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default:
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return (-1);
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}
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ret = sc->callfn(a0, a1, a2, 0, 0, 0, 0, 0, &res);
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return (ret);
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}
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int
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s10_svc_allocate_memory(device_t dev, struct s10_svc_mem *mem, int size)
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{
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struct s10_svc_softc *sc;
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sc = device_get_softc(dev);
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if (size <= 0)
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return (EINVAL);
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if (vmem_alloc(sc->vmem, size,
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M_FIRSTFIT | M_NOWAIT, &mem->paddr)) {
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device_printf(dev, "Can't allocate memory\n");
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return (ENOMEM);
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}
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mem->size = size;
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mem->fill = 0;
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mem->vaddr = (vm_offset_t)pmap_mapdev(mem->paddr, mem->size);
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return (0);
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}
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void
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s10_svc_free_memory(device_t dev, struct s10_svc_mem *mem)
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{
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struct s10_svc_softc *sc;
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sc = device_get_softc(dev);
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vmem_free(sc->vmem, mem->paddr, mem->size);
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}
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static int
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s10_get_memory(struct s10_svc_softc *sc)
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{
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struct arm_smccc_res res;
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vmem_addr_t addr;
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vmem_size_t size;
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vmem_t *vmem;
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sc->callfn(INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM,
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0, 0, 0, 0, 0, 0, 0, &res);
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if (res.a0 != INTEL_SIP_SMC_STATUS_OK)
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return (ENXIO);
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vmem = vmem_create("stratix10 vmem", 0, 0, PAGE_SIZE,
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PAGE_SIZE, M_BESTFIT | M_WAITOK);
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if (vmem == NULL)
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return (ENXIO);
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addr = res.a1;
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size = res.a2;
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device_printf(sc->dev, "Shared memory address 0x%lx size 0x%lx\n",
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addr, size);
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vmem_add(vmem, addr, size, 0);
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sc->vmem = vmem;
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return (0);
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}
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static intel_smc_callfn_t
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s10_svc_get_callfn(struct s10_svc_softc *sc, phandle_t node)
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{
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char method[16];
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if ((OF_getprop(node, "method", method, sizeof(method))) > 0) {
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if (strcmp(method, "hvc") == 0)
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return (arm_smccc_hvc);
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else if (strcmp(method, "smc") == 0)
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return (arm_smccc_smc);
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else
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device_printf(sc->dev,
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"Invalid method \"%s\"\n", method);
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} else
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device_printf(sc->dev, "SMC method not provided\n");
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return (NULL);
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}
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static int
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s10_svc_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "intel,stratix10-svc"))
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return (ENXIO);
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device_set_desc(dev, "Stratix 10 SVC");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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s10_svc_attach(device_t dev)
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{
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struct s10_svc_softc *sc;
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phandle_t node;
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node = ofw_bus_get_node(dev);
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (device_get_unit(dev) != 0)
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return (ENXIO);
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sc->callfn = s10_svc_get_callfn(sc, node);
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if (sc->callfn == NULL)
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return (ENXIO);
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if (s10_get_memory(sc) != 0)
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return (ENXIO);
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return (0);
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}
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static device_method_t s10_svc_methods[] = {
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DEVMETHOD(device_probe, s10_svc_probe),
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DEVMETHOD(device_attach, s10_svc_attach),
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{ 0, 0 }
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};
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static driver_t s10_svc_driver = {
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"s10_svc",
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s10_svc_methods,
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sizeof(struct s10_svc_softc),
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};
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static devclass_t s10_svc_devclass;
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EARLY_DRIVER_MODULE(s10_svc, firmware, s10_svc_driver,
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s10_svc_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
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