freebsd-dev/sys/dev/bhnd/cores
Landon J. Fuller caeff9a3c2 bhnd(4): implement MIPS and PCI(e) interrupt support
On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the
common bhnd(4) core drivers; we now register an INTRNG child PIC that
handles routing of backplane interrupt vectors via the MIPS core.

On BHND PCI devices, backplane interrupt vectors are now routed to the
PCI/PCIe host bridge core when bus_setup_intr() is called, where they are
dispatched by the PCI core via a host interrupt (e.g. INTx/MSI).

The bhndb(4) bridge driver tracks registered interrupt handlers for the
bridged bhnd(4) devices and manages backplane interrupt routing, while
delegating actual bus interrupt setup/teardown to the parent bus on behalf
of the bridged cores.

Approved by:	adrian (mentor, implicit)
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D12518
2017-11-21 23:15:20 +00:00
..
chipc bhnd(4): implement MIPS and PCI(e) interrupt support 2017-11-21 23:15:20 +00:00
pci bhnd(4): implement MIPS and PCI(e) interrupt support 2017-11-21 23:15:20 +00:00
pcie2 bhnd(4): Add a vendor parameter to BHND_DEVICE(), replacing vendor-specific 2016-06-08 21:31:33 +00:00
pmu bhnd: Implement bhnd(4) platform device registration. 2017-09-27 19:44:23 +00:00
usb bhnd(4): implement MIPS and PCI(e) interrupt support 2017-11-21 23:15:20 +00:00