Neel Natu d181963296 Optimize the common case of injecting an interrupt into a vcpu after a HLT ... by explicitly moving it out of the interrupt shadow. The hypervisor is done "executing" the HLT and by definition this moves the vcpu out of the 1-instruction interrupt shadow. Prior to this change the interrupt would be held pending because the VMCS guest-interruptibility-state would indicate that "blocking by STI" was in effect. This resulted in an unnecessary round trip into the guest before the pending interrupt could be injected. Reviewed by: grehan		2014-09-12 06:15:20 +00:00
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acpica	don't set CR4 PSE bit on amd64	2014-07-23 15:53:29 +00:00
amd64	MFamd64: Use initializecpu() to set various model-specific registers on	2014-09-10 21:37:47 +00:00
conf	Add mrsas(4) to GENERIC for i386 and amd64.	2014-09-04 21:06:33 +00:00
ia32	x86: Allow users to change PSL_RF via ptrace(PT_SETREGS...)	2013-11-14 15:37:20 +00:00
include	Optimize the common case of injecting an interrupt into a vcpu after a HLT	2014-09-12 06:15:20 +00:00
linux32	Revert r266925 as it can lead to instant panic at fexecve():	2014-06-17 05:29:18 +00:00
pci	Pull in r267961 and r267973 again. Fix for issues reported will follow.	2014-06-28 03:56:17 +00:00
vmm	Optimize the common case of injecting an interrupt into a vcpu after a HLT	2014-09-12 06:15:20 +00:00
Makefile	Adjustments to make a tags file a bit more suitable to amd64.	2008-12-01 14:15:10 +00:00