137 lines
4.1 KiB
Markdown
137 lines
4.1 KiB
Markdown
;; AMD K6/K6-2 Scheduling
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;; Copyright (C) 2002 ;; Free Software Foundation, Inc.
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;;
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;; This file is part of GNU CC.
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;;
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;; GNU CC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 2, or (at your option)
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;; any later version.
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;;
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;; GNU CC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GNU CC; see the file COPYING. If not, write to
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;; the Free Software Foundation, 59 Temple Place - Suite 330,
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;; Boston, MA 02111-1307, USA. */
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;;
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;; The K6 has similar architecture to PPro. Important difference is, that
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;; there are only two decoders and they seems to be much slower than execution
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;; units. So we have to pay much more attention to proper decoding for
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;; schedulers. We share most of scheduler code for PPro in i386.c
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;;
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;; The fp unit is not pipelined and do one operation per two cycles including
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;; the FXCH.
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;;
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;; alu describes both ALU units (ALU-X and ALU-Y).
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;; alux describes X alu unit
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;; fpu describes FPU unit
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;; load describes load unit.
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;; branch describes branch unit.
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;; store decsribes store unit. This unit is not modelled completely and only
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;; used to model lea operation. Otherwise it lie outside of the critical
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;; path.
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;;
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;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
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;; The decoder specification is in the PPro section above!
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;; Shift instructions and certain arithmetic are issued only to X pipe.
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(define_function_unit "k6_alux" 1 0
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot,cld"))
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1 1)
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;; The QI mode arithmetic is issued to X pipe only.
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(define_function_unit "k6_alux" 1 0
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec")
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(match_operand:QI 0 "general_operand" "")))
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1 1)
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(define_function_unit "k6_alu" 2 0
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
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1 1)
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(define_function_unit "k6_alu" 2 0
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "imov")
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(eq_attr "memory" "none")))
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1 1)
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(define_function_unit "k6_branch" 1 0
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "call,callv,ibr"))
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1 1)
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;; Load unit have two cycle latency, but we take care for it in adjust_cost
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(define_function_unit "k6_load" 1 0
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(and (eq_attr "cpu" "k6")
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(ior (eq_attr "type" "pop")
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(eq_attr "memory" "load,both")))
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1 1)
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(define_function_unit "k6_load" 1 0
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(and (eq_attr "cpu" "k6")
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(and (eq_attr "type" "str")
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(eq_attr "memory" "load,both")))
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10 10)
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;; Lea have two instructions, so latency is probably 2
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(define_function_unit "k6_store" 1 0
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "lea"))
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2 1)
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(define_function_unit "k6_store" 1 0
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "str"))
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10 10)
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(define_function_unit "k6_store" 1 0
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(and (eq_attr "cpu" "k6")
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(ior (eq_attr "type" "push")
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(eq_attr "memory" "store,both")))
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1 1)
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(define_function_unit "k6_fpu" 1 1
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "fop,fmov,fcmp,fistp"))
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2 2)
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(define_function_unit "k6_fpu" 1 1
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "fmul"))
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2 2)
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;; ??? Guess
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(define_function_unit "k6_fpu" 1 1
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "fdiv,fpspc"))
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56 56)
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(define_function_unit "k6_alu" 2 0
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "imul"))
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2 2)
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(define_function_unit "k6_alux" 1 0
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "imul"))
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2 2)
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;; ??? Guess
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(define_function_unit "k6_alu" 2 0
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "idiv"))
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17 17)
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(define_function_unit "k6_alux" 1 0
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(and (eq_attr "cpu" "k6")
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(eq_attr "type" "idiv"))
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17 17)
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